[U-Boot] [PATCH v2 2/5] spi: add spi-mem driver for MediaTek MT7629 SoC

[Weijie Gao <weijie.gao@mediatek.com>]

On Tue, 2019-05-07 at 18:42 +0530, Jagan Teki wrote:
> On Sun, May 5, 2019 at 2:59 PM Weijie Gao <weijie.gao@mediatek.com> wrote:
> >
> > This patch adds spi-mem driver for MediaTek MT7629 SoC to access SPI-NOR
> > and SPI-NAND flashes.
> >
> > Cc: Jagan Teki <jagan@openedev.com>
> > Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> > ---
> > Changes since v1: rename mtk_spimem to spi_snfi_spi. change pinctrl name.
> > ---
> >  drivers/spi/Kconfig        |   9 +
> >  drivers/spi/Makefile       |   1 +
> >  drivers/spi/mtk_snfi_spi.c | 325 +++++++++++++++++++++++++++++++++++++
> >  3 files changed, 335 insertions(+)
> >  create mode 100644 drivers/spi/mtk_snfi_spi.c
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > index 92d7ca6d8cb..a3feca97f59 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -139,6 +139,15 @@ config MT7621_SPI
> >           the SPI NOR flash on platforms embedding this Ralink / MediaTek
> >           SPI core, like MT7621/7628/7688.
> >
> > +config MTK_SNFI_SPI
> > +       bool "Mediatek SPI memory controller driver"
> > +       depends on SPI_MEM
> > +       help
> > +         Enable the Mediatek SPI memory controller driver. This driver is
> > +         originally based on the MediaTek SNFI IP core. It can only be
> > +         used to access SPI memory devices like SPI-NOR or SPI-NAND on
> > +         platforms embedding this IP core, like MT7622/M7629.
> > +
> >  config MVEBU_A3700_SPI
> >         bool "Marvell Armada 3700 SPI driver"
> >         select CLK_ARMADA_3720
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> > index f1e3becd2b7..5c639634777 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -36,6 +36,7 @@ obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
> >  obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
> >  obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
> >  obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
> > +obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
> >  obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
> >  obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
> >  obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
> > diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c
> > new file mode 100644
> > index 00000000000..230b7243d6f
> > --- /dev/null
> > +++ b/drivers/spi/mtk_snfi_spi.c
> > @@ -0,0 +1,325 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
> > + *
> > + * Author: Weijie Gao <weijie.gao@mediatek.com>
> > + */
> > +
> > +#include <common.h>
> > +#include <clk.h>
> > +#include <dm.h>
> > +#include <errno.h>
> > +#include <spi.h>
> > +#include <spi-mem.h>
> > +#include <stdbool.h>
> > +#include <dm/pinctrl.h>
> > +#include <linux/bitops.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +
> > +#define SNFI_MAC_CTL                   0x500
> > +#define MAC_XIO_SEL                    BIT(4)
> > +#define SF_MAC_EN                      BIT(3)
> > +#define SF_TRIG                                BIT(2)
> > +#define WIP_READY                      BIT(1)
> > +#define WIP                            BIT(0)
> > +
> > +#define SNFI_MAC_OUTL                  0x504
> > +#define SNFI_MAC_INL                   0x508
> > +
> > +#define SNFI_MISC_CTL                  0x538
> > +#define SW_RST                         BIT(28)
> > +#define FIFO_RD_LTC_SHIFT              25
> > +#define FIFO_RD_LTC                    GENMASK(26, 25)
> > +#define LATCH_LAT_SHIFT                        8
> > +#define LATCH_LAT                      GENMASK(9, 8)
> > +#define CS_DESELECT_CYC_SHIFT          0
> > +#define CS_DESELECT_CYC                        GENMASK(4, 0)
> > +
> > +#define SNF_STA_CTL1                   0x550
> > +#define SPI_STATE                      GENMASK(3, 0)
> > +
> > +#define SNFI_GPRAM_OFFSET              0x800
> > +#define SNFI_GPRAM_SIZE                        0x80
> > +
> > +#define SNFI_POLL_INTERVAL             500000
> > +#define SNFI_RST_POLL_INTERVAL         1000000
> > +
> > +struct mtk_snfi_priv {
> > +       void __iomem *base;
> > +
> > +       struct udevice *dev;
> 
> Do we really need this dev? seems like you are passing priv and get
> the dev, why can't you pass the dev directly?
> 
> Look like it is not possible since the spi_mem ops not using udevice,
> did you observed this?

The dev in the priv struct is a mistake. It will be removed.

spi_mem_ops is only a subset of dm_spi_ops, which means there must be a
spi udevice for the spi slave device. I've checked source codes for both
spi-uclass.c, sf-uclass.c, sf_probe.c and spi-nor-core.c and I'm sure
udevice is available by referencing from spi_slave.