From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ley Foon Tan Date: Thu, 30 May 2019 17:03:30 +0800 Subject: [U-Boot] [PATCH 01/15] arm: socfpga: agilex: Add base address for Intel Agilex SoC In-Reply-To: <1559207024-22181-1-git-send-email-ley.foon.tan@intel.com> References: <1559207024-22181-1-git-send-email-ley.foon.tan@intel.com> Message-ID: <1559207024-22181-2-git-send-email-ley.foon.tan@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add base address for Intel Agilex SoC. Reuse base_addr_s10.h for Agilex, only one base address is different from S10. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h index 1f549d7e70..d3eca65e97 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -10,7 +10,11 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 +#else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 +#endif #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 -- 2.19.0