From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eddie James Date: Thu, 15 Aug 2019 14:29:37 -0500 Subject: [U-Boot] [PATCH v3 1/4] clk: aspeed: Add support for SD clock In-Reply-To: <1565897380-25807-1-git-send-email-eajames@linux.ibm.com> References: <1565897380-25807-1-git-send-email-eajames@linux.ibm.com> Message-ID: <1565897380-25807-2-git-send-email-eajames@linux.ibm.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Eddie James --- arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 3 +++ drivers/clk/aspeed/clk_ast2500.c | 27 ++++++++++++++++++++++= ++++ drivers/pinctrl/aspeed/pinctrl_ast2500.c | 2 ++ 3 files changed, 32 insertions(+) diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/incl= ude/asm/arch-aspeed/scu_ast2500.h index 4988ced..8db4901 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -22,6 +22,8 @@ #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) #define SCU_PCLK_DIV_SHIFT 23 #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) +#define SCU_SDCLK_DIV_SHIFT 12 +#define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT) #define SCU_HPLL_DENUM_SHIFT 0 #define SCU_HPLL_DENUM_MASK 0x1f #define SCU_HPLL_NUM_SHIFT 5 @@ -107,6 +109,7 @@ =20 #define SCU_CLKSTOP_MAC1 (1 << 20) #define SCU_CLKSTOP_MAC2 (1 << 21) +#define SCU_CLKSTOP_SDCLK (1 << 27) =20 #define SCU_D2PLL_EXT1_OFF (1 << 0) #define SCU_D2PLL_EXT1_BYPASS (1 << 1) diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2= 500.c index dbee13a..9249cf9 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -143,6 +143,17 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate =3D rate / apb_div; } break; + case BCLK_SDCLK: + { + ulong apb_div =3D 4 + 4 * ((readl(&priv->scu->clk_sel1) + & SCU_SDCLK_DIV_MASK) + >> SCU_SDCLK_DIV_SHIFT); + rate =3D ast2500_get_hpll_rate(clkin, + readl(&priv-> + scu->h_pll_param)); + rate =3D rate / apb_div; + } + break; case PCLK_UART1: rate =3D ast2500_get_uart_clk_rate(priv->scu, 1); break; @@ -436,6 +447,22 @@ static int ast2500_clk_enable(struct clk *clk) struct ast2500_clk_priv *priv =3D dev_get_priv(clk->dev); =20 switch (clk->id) { + case BCLK_SDCLK: + if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) { + ast_scu_unlock(priv->scu); + + setbits_le32(&priv->scu->sysreset_ctrl1, + SCU_SYSRESET_SDIO); + udelay(100); + clrbits_le32(&priv->scu->clk_stop_ctrl1, + SCU_CLKSTOP_SDCLK); + mdelay(10); + clrbits_le32(&priv->scu->sysreset_ctrl1, + SCU_SYSRESET_SDIO); + + ast_scu_lock(priv->scu); + } + break; /* * For MAC clocks the clock rate is * configured based on whether RGMII or RMII mode has been selected diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c b/drivers/pinctrl/asp= eed/pinctrl_ast2500.c index ed333b9..a6e9c0d 100644 --- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c +++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c @@ -58,6 +58,8 @@ static const struct ast2500_group_config ast2500_groups[]= =3D { { "MDIO1", 3, (1 << 31) | (1 << 30) }, { "MAC2LINK", 1, (1 << 1) }, { "MDIO2", 5, (1 << 2) }, + { "SD1", 5, (1 << 0) }, + { "SD2", 5, (1 << 1) }, }; =20 static int ast2500_pinctrl_get_groups_count(struct udevice *dev) --=20 1.8.3.1