From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kurt Miller Date: Mon, 19 Aug 2019 19:32:04 -0400 Subject: [U-Boot] Rockpro64_V2.1 2018-07-02 Boot Freeze In-Reply-To: References: <1565991886.11007.28.camel@intricatesoftware.com> <1566223437.11007.33.camel@intricatesoftware.com> <1566227577.11007.35.camel@intricatesoftware.com> <1566234430.11007.49.camel@intricatesoftware.com> Message-ID: <1566257524.11007.92.camel@intricatesoftware.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de Hi Jagan, On Mon, 2019-08-19 at 23:26 +0530, Jagan Teki wrote: > Is your board running at 50MHz? (look like No). No it is running at 800Mhz or 856MHz (see rkbin TPL output below). > As I said please > explore step-by-step > 00: First boot the board rkbin => SPL => U-Boot proper This step was completed already. Here is the output again for reference: DDR Version 1.23 20190709                                                     In                                                                            channel 0                                                                     CS = 0                                                                        MR0=0xB8                                                                      MR4=0x1                                  MR5=0xFF                                 MR8=0x10                                 MR12=0x72                                MR14=0x72                                MR18=0x0                                 MR19=0x0 MR24=0x8 MR25=0x0 channel 1 CS = 0 MR0=0xB8 MR4=0x1 MR5=0xFF MR8=0x10 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 0 training pass! channel 1 training pass! change freq to 416MHz 0,1 Channel 0: LPDDR4,416MHz Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB Channel 1: LPDDR4,416MHz Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB 256B stride channel 0 CS = 0 MR0=0xB8 MR4=0x1 MR5=0xFF MR8=0x10 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 1 CS = 0 MR0=0xB8 MR4=0x1 MR5=0xFF MR8=0x10 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 0 training pass! channel 1 training pass! channel 0, cs 0, advanced training done channel 1, cs 0, advanced training done change freq to 856MHz 1,0 ch 0 ddrconfig = 0x101, ddrsize = 0x40 ch 1 ddrconfig = 0x101, ddrsize = 0x40 pmugrf_os_reg[2] = 0x32C1F2C1, stride = 0xD OUT > 01: Grab the sdram-*.dtsi (steps mentioned in previous mail) and > replace rkbin withTPL I am stuck here. I see that there were three 800Mhz entries in the rkbin rk3399_ddr_800MHz_v1.20.bin file that was used to create ./arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi. rk3399-sdram-lpddr4-100.dtsi has one entry that appears to be from the first 800Mhz data in rk3399_ddr_800MHz_v1.20.bin. Using the instructions you linked: https://wiki.amarulasolutions.com/found/target/rk3399_sdram.html I have inspected rkbin rk3399_ddr_800MHz_v1.23.bin and found there are two 800Mhz entries in it. I have extracted the two entries but have have questions that the instructions don't address well. Why does the existing rk3399-sdram-lpddr4-100.dtsi only have one entry while the instructions appear to indicate there should be two, one for single and another for dual ranked? Step 6 refers to editing the dtsi file: "..., edit the initial values (don’t forget that they are in little endian form) to match what the SPL code expects,  convert the frequency value from the binary back into MHz (line 38 in the attached dtsi files for reference)" I believe I was able to convert the data into the updated values correctly (see attached diff). However, one value stood out to me. The 800Mhz value of 0x2faf0800 was converted into decimal 50 in the existing data whereas other sdram files converted it into 1/2 the Mhz value (e.g. 800Mhz -> 400). With it set to 50 I get this output before it stops: U-Boot TPL 2019.10-rc2-00016-g81fed78c0a-dirty (Aug 19 2019 - 18:45:16)          pctl_start: Failed to init pctl for channel 0  With it set to 400 I get this output before it stops: U-Boot TPL 2019.10-rc2-00016-g81fed78c0a-dirty (Aug 19 2019 - 19:14:10)       sdram_init: DDR3 - 400MHz failed!                                             rk3399_dmc_init DRAM init failed -22                                          Missing DTB  > 02: Then dump the regmap if 01 failed. > > Jagan. 01 failed. With the timings diff reverted I get this before it freezes: U-Boot TPL 2019.10-rc2-00016-g81fed78c0a-dirty (Aug 19 2019 - 12:57:39)       LPDDR4, 50MHz                                                                 BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB                       LPDDR4, 50MHz                                                                 BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB 256B stride                              cic: ctr10: (0xff620000 - 0x14)          cic: status0: (0xff620010 - 0x101)       grf: ddrc0_con0 (0xff77e380 - 0x1f81)    grf: ddrc1_con0 (0xff77e388 - 0x1f81)    grf: soc_con0 (0xff77e200 - 0x7) pmu: noc_auto_ena (0xff3100d8 - 0x0) pmu: bus_idle_req (0xff310060 - 0x0) pmu: bus_idle_st (0xff310064 - 0x0) pmugrf: os_reg2 (0xff320308 - 0x32a1f2a1) pmugrf: os_reg3 (0xff32030c - 0x20000005) pmusgrf: soc_con4 (0xff33e010 - 0x2600) Please let me know other items can be tried to get this up and running with the U-Boot TPL. Regards, -Kurt -------------- next part -------------- A non-text attachment was scrubbed... Name: timings.diff Type: text/x-patch Size: 17666 bytes Desc: not available URL: