[U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected

[Kurt Miller <lists@intricatesoftware.com>]

Re-testing with master as of Sep 12 and the wrong memory
size continues to be detected (2G detected while the
board has 4G).

The board has the following marking on it:

Rockpro64_V2.1 2018-07-02

RAM Chips:
PS052-053 BT
83RL

I'd be happy to test any proposed patches to correct
the memory size detection on this board.

On Wed, 2019-08-28 at 17:45 -0400, Kurt Miller wrote:
> The board has 4G memory but only 2G is detected by TPL. Please
> let me know if additional information is needed.
> 
> With u-boot master TPL output:
> 
> U-Boot TPL 2019.10-rc3-00020-ge4b8dd9b34-dirty (Aug 28 2019 - 17:26:44)
> LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> 256B stride
> Trying to boot from BOOTROM
> Returning to boot ROM...
> 
> With rkbin rk3399_ddr_800MHz_v1.23.bin output:
> 
> DDR Version 1.23 20190709                                                    
> In                                                                           
> channel 0                                                                    
> CS = 0                                                                       
> MR0=0xB8                                                                     
> MR4=0x2                                 
> MR5=0xFF                                
> MR8=0x10                                
> MR12=0x72                               
> MR14=0x72                               
> MR18=0x0                                
> MR19=0x0
> MR24=0x8
> MR25=0x0
> channel 1
> CS = 0
> MR0=0xB8
> MR4=0x2
> MR5=0xFF
> MR8=0x10
> MR12=0x72
> MR14=0x72
> MR18=0x0
> MR19=0x0
> MR24=0x8
> MR25=0x0
> channel 0 training pass!
> channel 1 training pass!
> change freq to 416MHz 0,1
> Channel 0: LPDDR4,416MHz
> Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
> Channel 1: LPDDR4,416MHz
> Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
> 256B stride
> channel 0
> CS = 0
> MR0=0xB8
> MR4=0x2
> MR5=0xFF
> MR8=0x10
> MR12=0x72
> MR14=0x72
> MR18=0x0
> MR19=0x0
> MR24=0x8
> MR25=0x0
> channel 1
> CS = 0
> MR0=0xB8
> MR4=0x2
> MR5=0xFF
> MR8=0x10
> MR12=0x72
> MR14=0x72
> MR18=0x0
> MR19=0x0
> MR24=0x8
> MR25=0x0
> channel 0 training pass!
> channel 1 training pass!
> channel 0, cs 0, advanced training done
> channel 1, cs 0, advanced training done
> change freq to 856MHz 1,0
> ch 0 ddrconfig = 0x101, ddrsize = 0x40
> ch 1 ddrconfig = 0x101, ddrsize = 0x40
> pmugrf_os_reg[2] = 0x32C1F2C1, stride = 0xD
> OUT