From: Ley Foon Tan <ley.foon.tan@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v8 10/19] arm: socfpga: agilex: Add clock wrapper functions
Date: Wed, 27 Nov 2019 15:55:23 +0800 [thread overview]
Message-ID: <1574841332-8977-11-git-send-email-ley.foon.tan@intel.com> (raw)
In-Reply-To: <1574841332-8977-1-git-send-email-ley.foon.tan@intel.com>
Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
v6:
- Use new macro names from agilex-clock.h.
v4:
- Change to use SYSMGR_SOC64* prefix.
v3:
- Improved commit message.
- Rename STRATIX10_* to SOCFPGA_SOC64_*
- Include clock_manager_soc64.h and clk-agilex.h.
v2:
- Get clocks from clock DM.
---
arch/arm/mach-socfpga/Makefile | 4 +
arch/arm/mach-socfpga/clock_manager_agilex.c | 85 +++++++++++++++++++
.../mach-socfpga/include/mach/clock_manager.h | 2 +
.../include/mach/clock_manager_agilex.h | 14 +++
4 files changed, 105 insertions(+)
create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index dab34d0ef2..a403b46b47 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -39,6 +39,10 @@ obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y += clock_manager_agilex.o
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c
new file mode 100644
index 0000000000..791066d25b
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/agilex-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+ struct udevice *dev;
+ struct clk clk;
+ ulong rate;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(socfpga_agilex_clk),
+ &dev);
+ if (ret)
+ return 0;
+
+ clk.id = id;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ return 0;
+
+ rate = clk_get_rate(&clk);
+
+ clk_free(&clk);
+
+ if ((rate == (unsigned long)-ENOSYS) ||
+ (rate == (unsigned long)-ENXIO) ||
+ (rate == (unsigned long)-EIO)) {
+ debug("%s id %u: clk_get_rate err: %ld\n",
+ __func__, id, rate);
+ return 0;
+ }
+
+ return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+ return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ return cm_get_rate_dm(AGILEX_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+ return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+}
+
+u32 cm_get_qspi_controller_clk_hz(void)
+{
+ return readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+ printf("MPU %10d kHz\n",
+ cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+ printf("L4 Main %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+ printf("L4 sys free %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+ printf("L4 MP %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+ printf("L4 SP %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+ printf("SDMMC %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 6de7caef19..c6830582a5 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -20,6 +20,8 @@ void cm_print_clock_quick_summary(void);
#include <asm/arch/clock_manager_arria10.h>
#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
#include <asm/arch/clock_manager_s10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#include <asm/arch/clock_manager_agilex.h>
#endif
#endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
new file mode 100644
index 0000000000..386e82a4e3
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLOCK_MANAGER_AGILEX_
+#define _CLOCK_MANAGER_AGILEX_
+
+unsigned long cm_get_mpu_clk_hz(void);
+
+#include <asm/arch/clock_manager_soc64.h>
+#include "../../../../../drivers/clk/altera/clk-agilex.h"
+
+#endif /* _CLOCK_MANAGER_AGILEX_ */
--
2.19.0
next prev parent reply other threads:[~2019-11-27 7:55 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-27 7:55 [U-Boot] [PATCH v8 00/19] Add Intel Agilex SoC support Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 01/19] arm: socfpga: agilex: Add base address for Intel Agilex SoC Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 02/19] arm: socfpga: Move firewall code to firewall file Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 03/19] arm: socfpga: Move Stratix10 and Agilex reset manager common code Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 04/19] arm: socfpga: agilex: Add reset manager support Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 05/19] arm: socfpga: Move Stratix10 and Agilex system manager common code Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 06/19] arm: socfpga: agilex: Add system manager support Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 08/19] arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 09/19] clk: agilex: Add clock driver for Agilex Ley Foon Tan
2019-11-27 7:55 ` Ley Foon Tan [this message]
2019-11-27 7:55 ` [U-Boot] [PATCH v8 11/19] cache: Add Arteris Ncore cache coherent unit driver Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 12/19] arm: agilex: Add clock handoff offset for Agilex Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 13/19] ddr: altera: Restructure Stratix 10 SDRAM driver Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 14/19] ddr: altera: agilex: Add SDRAM driver for Agilex Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 15/19] board: intel: agilex: Add socdk board support for Intel Agilex SoC Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 16/19] arm: socfpga: agilex: Add SPL for " Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 17/19] arm: dts: agilex: Add base dtsi and devkit dts Ley Foon Tan
2019-11-27 10:24 ` Simon Goldschmidt
2019-11-28 7:21 ` Ley Foon Tan
2019-11-28 7:28 ` Simon Goldschmidt
2019-11-28 7:33 ` Ley Foon Tan
2019-11-28 7:31 ` Ley Foon Tan
2019-11-28 7:34 ` Simon Goldschmidt
2019-11-27 7:55 ` [U-Boot] [PATCH v8 18/19] configs: socfpga: Move Stratix10 and Agilex common CONFIGs Ley Foon Tan
2019-11-27 19:27 ` Simon Goldschmidt
2019-11-27 7:55 ` [U-Boot] [PATCH v8 19/19] arm: socfpga: agilex: Enable Agilex SoC build Ley Foon Tan
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