From: Ley Foon Tan <ley.foon.tan@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v8 07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Date: Wed, 27 Nov 2019 15:55:20 +0800 [thread overview]
Message-ID: <1574841332-8977-8-git-send-email-ley.foon.tan@intel.com> (raw)
In-Reply-To: <1574841332-8977-1-git-send-email-ley.foon.tan@intel.com>
Move Stratix10 and Agilex clock manager common code to new header file.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
v6:
- Move #include <asm/arch/clock_manager_soc64.h> to top of header file.
v5:
- Revert CLKMGR_INTOSC_HZ to 460MHz.
---
.../include/mach/clock_manager_s10.h | 16 +++----------
.../include/mach/clock_manager_soc64.h | 23 +++++++++++++++++++
2 files changed, 26 insertions(+), 13 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 13eb23569c..e710aa2f94 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -1,12 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
*
*/
#ifndef _CLOCK_MANAGER_S10_
#define _CLOCK_MANAGER_S10_
+#include <asm/arch/clock_manager_soc64.h>
+
/* Clock speed accessors */
unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
@@ -14,18 +16,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
-const unsigned int cm_get_osc_clk_hz(void);
-const unsigned int cm_get_f2s_per_ref_clk_hz(void);
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
-const unsigned int cm_get_intosc_clk_hz(void);
-const unsigned int cm_get_fpga_clk_hz(void);
-
-#define CLKMGR_EOSC1_HZ 25000000
-#define CLKMGR_INTOSC_HZ 460000000
-#define CLKMGR_FPGA_CLK_HZ 50000000
-
-/* Clock configuration accessors */
-const struct cm_config * const cm_get_default_config(void);
struct cm_config {
/* main group */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
new file mode 100644
index 0000000000..3b4bb62ca5
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _CLOCK_MANAGER_SOC64_
+#define _CLOCK_MANAGER_SOC64_
+
+const unsigned int cm_get_osc_clk_hz(void);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+#define CLKMGR_EOSC1_HZ 25000000
+#define CLKMGR_INTOSC_HZ 460000000
+#define CLKMGR_FPGA_CLK_HZ 50000000
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+#endif /* _CLOCK_MANAGER_SOC64_ */
--
2.19.0
next prev parent reply other threads:[~2019-11-27 7:55 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-27 7:55 [U-Boot] [PATCH v8 00/19] Add Intel Agilex SoC support Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 01/19] arm: socfpga: agilex: Add base address for Intel Agilex SoC Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 02/19] arm: socfpga: Move firewall code to firewall file Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 03/19] arm: socfpga: Move Stratix10 and Agilex reset manager common code Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 04/19] arm: socfpga: agilex: Add reset manager support Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 05/19] arm: socfpga: Move Stratix10 and Agilex system manager common code Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 06/19] arm: socfpga: agilex: Add system manager support Ley Foon Tan
2019-11-27 7:55 ` Ley Foon Tan [this message]
2019-11-27 7:55 ` [U-Boot] [PATCH v8 08/19] arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 09/19] clk: agilex: Add clock driver for Agilex Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 10/19] arm: socfpga: agilex: Add clock wrapper functions Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 11/19] cache: Add Arteris Ncore cache coherent unit driver Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 12/19] arm: agilex: Add clock handoff offset for Agilex Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 13/19] ddr: altera: Restructure Stratix 10 SDRAM driver Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 14/19] ddr: altera: agilex: Add SDRAM driver for Agilex Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 15/19] board: intel: agilex: Add socdk board support for Intel Agilex SoC Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 16/19] arm: socfpga: agilex: Add SPL for " Ley Foon Tan
2019-11-27 7:55 ` [U-Boot] [PATCH v8 17/19] arm: dts: agilex: Add base dtsi and devkit dts Ley Foon Tan
2019-11-27 10:24 ` Simon Goldschmidt
2019-11-28 7:21 ` Ley Foon Tan
2019-11-28 7:28 ` Simon Goldschmidt
2019-11-28 7:33 ` Ley Foon Tan
2019-11-28 7:31 ` Ley Foon Tan
2019-11-28 7:34 ` Simon Goldschmidt
2019-11-27 7:55 ` [U-Boot] [PATCH v8 18/19] configs: socfpga: Move Stratix10 and Agilex common CONFIGs Ley Foon Tan
2019-11-27 19:27 ` Simon Goldschmidt
2019-11-27 7:55 ` [U-Boot] [PATCH v8 19/19] arm: socfpga: agilex: Enable Agilex SoC build Ley Foon Tan
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