[PATCH] rockchip: Add delay after link-training

[Kurt Miller <kurt@intricatesoftware.com>]

On Tue, 2020-06-02 at 02:16 +0530, Jagan Teki wrote:
> On Tue, Jun 2, 2020 at 2:00 AM Kurt Miller <kurt@intricatesoftware.com> wrote:
> > 
> > 
> > On at least the RockPro64, many cards will trip a
> > synchronous abort when first accessing PCIe config space
> > during bus scanning. A delay after link training allows
> > some of these cards to function.
> Can you check does the SoC has external PCIe pwr-pin GPIO?
> 
> I did see unstable SSD behavior on rock960 but fixed with this.
> https://github.com/radxa/u-boot/blob/stable-4.4-rockpi4/board/rockchip/evb_rk3399/evb-rk3399.c#L168

The schematic has:

GPIO1_D0/TCPD_VBUS_SOURCE2_d ---L26---->>PCIE_PWR

and?arch/arm/dts/rk3399-rockpro64.dtsi has:

&pinctrl {
? ? ? ? pcie {
? ? ? ? ? ? ? ? pcie_pwr_en: pcie-pwr-en {
????????????????????????rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
????????????????};
????????};
};

Does that answer your question? I'm rather new at this so
I may need more guidance if I miss understood your question.

Thanks,
-Kurt