[PATCH v2 04/11] reset: add basic reset controller for pciesys

[Sam Shih <sam.shih@mediatek.com>]

Hi Frank,

Thanks your for your patches.
some suggestions for coding style.


On Wed, 2020-08-19 at 10:02 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> bind reset controller to pciesys
> 
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
>  drivers/clk/mediatek/clk-mt7622.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
> index bd86b5b974..d53ed69189 100644
> --- a/drivers/clk/mediatek/clk-mt7622.c
> +++ b/drivers/clk/mediatek/clk-mt7622.c
> @@ -594,6 +594,20 @@ static int mt7622_pciesys_probe(struct udevice *dev)
>  	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
>  }
>  
> +static int mt7622_pciesys_bind(struct udevice *dev)
> +{
> +	int ret = 0;
> +
> +	if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
> +//	PCIESYS uses in linux also 0x34 = ETHSYS reset controller

No need to add special comments that are not easy to understand,
and please uses "/* */" instead of "//".

Thanks,
Best Regards,
Sam Shih