[U-Boot] [PATCH v2 1/2] gpio: Add GPIO driver framework for Marvell SoCs

[Ajay Bhargav <ajay.bhargav@einfochips.com>]

----- "Simon Guinot" <simon@sequanux.org> wrote:

> AFAIK, Orion and Kirkwood SoCs don't provide bitwise set/clear for
> GPIO output/direction registers. Instead, a register must be read
> first to leave other bits unchanged (see __set_direction in
> kw_gpio.c).
> 
> Is it possible to handle Armada SoCs GPIOs in a same way ? maybe
> using
> the pin registers (gpxx in the Armada struct gpio_reg array) ?
> 
> If not, this code is not Marvell generic but rather specific for
> Armada
> SoCs and then maybe armada_gpio is a better name...
> 
> Regards,
> 
> Simon

Hi Simon,

Yes its possible to implement code that way, Armada SoC does have GPIO
registers for set/clear. what about register naming?? I think they are
different for Kirkwood and Orion.

One more thing which can be done to make this code generic is to have
some macros which can be defined by individual arch for specific registers
which are going to be in use e.g.

#define GPIO_PIN_LEVEL_REG
#define GPIO_DIR_REG
#define GPIO_PIN_SET_REG
#define GPIO_PIN_CLR_REG

so anyone can have their own version of these registers in gpio.h of their
arch. The only thing which can complicate this is banking of registers, no.
of banks etc.

Please provide comments on this, so we can have a better code.

Thanks & Regards,
Ajay Bhargav