* [U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5
@ 2013-02-06 21:37 Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 2/9] nand: mxc: Add " Benoît Thébaudeau
` (7 more replies)
0 siblings, 8 replies; 10+ messages in thread
From: Benoît Thébaudeau @ 2013-02-06 21:37 UTC (permalink / raw)
To: u-boot
Add some abstraction to NFC defitnitions so that some parts of the current code
can also be used for future i.MX5 code.
Clean up a few things by the way.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
Changes in v4: None
Changes in v3:
- Separate code reformatting from behavioral changes.
Changes in v2:
- Fix warning for unused tmp variable in board_nand_init() for NFC V1.
drivers/mtd/nand/mxc_nand.c | 92 +++++++++++++++++++++---------------------
include/fsl_nfc.h | 72 ++++++++++++---------------------
nand_spl/nand_boot_fsl_nfc.c | 47 +++++++++++----------
3 files changed, 97 insertions(+), 114 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index d0ded48..045df49 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -150,7 +150,7 @@ static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size
/*
* This function polls the NANDFC to wait for the basic operation to
- * complete by checking the INT bit of config2 register.
+ * complete by checking the INT bit.
*/
static void wait_op_done(struct mxc_nand_host *host, int max_retries,
uint16_t param)
@@ -158,10 +158,10 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries,
uint32_t tmp;
while (max_retries-- > 0) {
- if (readw(&host->regs->config2) & NFC_INT) {
- tmp = readw(&host->regs->config2);
- tmp &= ~NFC_INT;
- writew(tmp, &host->regs->config2);
+ tmp = readnfc(&host->regs->config2);
+ if (tmp & NFC_V1_V2_CONFIG2_INT) {
+ tmp &= ~NFC_V1_V2_CONFIG2_INT;
+ writenfc(tmp, &host->regs->config2);
break;
}
udelay(1);
@@ -180,8 +180,8 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
- writew(cmd, &host->regs->flash_cmd);
- writew(NFC_CMD, &host->regs->config2);
+ writenfc(cmd, &host->regs->flash_cmd);
+ writenfc(NFC_CMD, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, cmd);
@@ -196,8 +196,8 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr)
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
- writew(addr, &host->regs->flash_addr);
- writew(NFC_ADDR, &host->regs->config2);
+ writenfc(addr, &host->regs->flash_addr);
+ writenfc(NFC_ADDR, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, addr);
@@ -229,19 +229,19 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
}
}
- writew(buf_id, &host->regs->buf_addr);
+ writenfc(buf_id, &host->regs->buf_addr);
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint16_t config1 = readw(&host->regs->config1);
+ uint16_t config1 = readnfc(&host->regs->config1);
if (spare_only)
- config1 |= NFC_SP_EN;
+ config1 |= NFC_CONFIG1_SP_EN;
else
- config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->config1);
+ config1 &= ~NFC_CONFIG1_SP_EN;
+ writenfc(config1, &host->regs->config1);
}
- writew(NFC_INPUT, &host->regs->config2);
+ writenfc(NFC_INPUT, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
@@ -256,19 +256,19 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
- writew(buf_id, &host->regs->buf_addr);
+ writenfc(buf_id, &host->regs->buf_addr);
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint32_t config1 = readw(&host->regs->config1);
+ uint32_t config1 = readnfc(&host->regs->config1);
if (spare_only)
- config1 |= NFC_SP_EN;
+ config1 |= NFC_CONFIG1_SP_EN;
else
- config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->config1);
+ config1 &= ~NFC_CONFIG1_SP_EN;
+ writenfc(config1, &host->regs->config1);
}
- writew(NFC_OUTPUT, &host->regs->config2);
+ writenfc(NFC_OUTPUT, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
@@ -296,14 +296,14 @@ static void send_read_id(struct mxc_nand_host *host)
uint16_t tmp;
/* NANDFC buffer 0 is used for device ID output */
- writew(0x0, &host->regs->buf_addr);
+ writenfc(0x0, &host->regs->buf_addr);
/* Read ID into main buffer */
- tmp = readw(&host->regs->config1);
- tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->config1);
+ tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_CONFIG1_SP_EN;
+ writenfc(tmp, &host->regs->config1);
- writew(NFC_ID, &host->regs->config2);
+ writenfc(NFC_ID, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
@@ -323,14 +323,14 @@ static uint16_t get_dev_status(struct mxc_nand_host *host)
/* store the main area1 first word, later do recovery */
store = readl(main_buf);
/* NANDFC buffer 1 is used for device status */
- writew(1, &host->regs->buf_addr);
+ writenfc(1, &host->regs->buf_addr);
/* Read status into main buffer */
- tmp = readw(&host->regs->config1);
- tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->config1);
+ tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_CONFIG1_SP_EN;
+ writenfc(tmp, &host->regs->config1);
- writew(NFC_STATUS, &host->regs->config2);
+ writenfc(NFC_STATUS, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
@@ -359,13 +359,13 @@ static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- uint16_t tmp = readw(&host->regs->config1);
+ uint16_t tmp = readnfc(&host->regs->config1);
if (on)
- tmp |= NFC_ECC_EN;
+ tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
else
- tmp &= ~NFC_ECC_EN;
- writew(tmp, &host->regs->config1);
+ tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
+ writenfc(tmp, &host->regs->config1);
}
#ifdef CONFIG_MXC_NAND_HWECC
@@ -698,7 +698,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
* additional correction. 2-Bit errors cannot be corrected by
* HW ECC, so we need to return failure
*/
- uint16_t ecc_status = readw(&host->regs->ecc_status_result);
+ uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
MTDDEBUG(MTD_DEBUG_LEVEL0,
@@ -1241,24 +1241,24 @@ int board_nand_init(struct nand_chip *this)
#endif
#ifdef MXC_NFC_V2_1
- tmp = readw(&host->regs->config1);
- tmp |= NFC_ONE_CYCLE;
- tmp |= NFC_4_8N_ECC;
- writew(tmp, &host->regs->config1);
+ tmp = readnfc(&host->regs->config1);
+ tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
+ tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
+ writenfc(tmp, &host->regs->config1);
if (host->pagesize_2k)
- writew(64/2, &host->regs->spare_area_size);
+ writenfc(64/2, &host->regs->spare_area_size);
else
- writew(16/2, &host->regs->spare_area_size);
+ writenfc(16/2, &host->regs->spare_area_size);
#endif
/*
* preset operation
* Unlock the internal RAM Buffer
*/
- writew(0x2, &host->regs->config);
+ writenfc(0x2, &host->regs->config);
/* Blocks to be unlocked */
- writew(0x0, &host->regs->unlockstart_blkaddr);
+ writenfc(0x0, &host->regs->unlockstart_blkaddr);
/* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
* unlockend_blkaddr, but the magic 0x4000 does not always work
* when writing more than some 32 megabytes (on 2k page nands)
@@ -1270,10 +1270,10 @@ int board_nand_init(struct nand_chip *this)
* This might be NAND chip specific and the i.MX31 datasheet is
* extremely vague about the semantics of this register.
*/
- writew(0xFFFF, &host->regs->unlockend_blkaddr);
+ writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
/* Unlock Block Command for given address range */
- writew(0x4, &host->regs->wrprot);
+ writenfc(0x4, &host->regs->wrprot);
return 0;
}
diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h
index ff537b4..013e9e2 100644
--- a/include/fsl_nfc.h
+++ b/include/fsl_nfc.h
@@ -113,58 +113,38 @@ struct fsl_nfc_regs {
#endif
};
-/*
- * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
- * operation
- */
-#define NFC_CMD 0x1
+/* Set FCMD to 1, rest to 0 for Command operation */
+#define NFC_CMD 0x1
-/*
- * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
- * operation
- */
-#define NFC_ADDR 0x2
+/* Set FADD to 1, rest to 0 for Address operation */
+#define NFC_ADDR 0x2
-/*
- * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
- * operation
- */
-#define NFC_INPUT 0x4
+/* Set FDI to 1, rest to 0 for Input operation */
+#define NFC_INPUT 0x4
-/*
- * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
- * Output operation
- */
-#define NFC_OUTPUT 0x8
+/* Set FDO to 001, rest to 0 for Data Output operation */
+#define NFC_OUTPUT 0x8
-/*
- * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
- * operation
- */
-#define NFC_ID 0x10
+/* Set FDO to 010, rest to 0 for Read ID operation */
+#define NFC_ID 0x10
-/*
- * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
- * Status operation
- */
-#define NFC_STATUS 0x20
+/* Set FDO to 100, rest to 0 for Read Status operation */
+#define NFC_STATUS 0x20
-/*
- * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
- * operation
- */
-#define NFC_INT 0x8000
+#define NFC_CONFIG1_SP_EN (1 << 2)
+#define NFC_CONFIG1_RST (1 << 6)
+#define NFC_CONFIG1_CE (1 << 7)
+#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
+#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
+#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
+#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
+#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
+#define NFC_V2_CONFIG1_FP_INT (1 << 11)
-#ifdef MXC_NFC_V2_1
-#define NFC_4_8N_ECC (1 << 0)
-#endif
-#define NFC_SP_EN (1 << 2)
-#define NFC_ECC_EN (1 << 3)
-#define NFC_INT_MSK (1 << 4)
-#define NFC_BIG (1 << 5)
-#define NFC_RST (1 << 6)
-#define NFC_CE (1 << 7)
-#define NFC_ONE_CYCLE (1 << 8)
-#define NFC_FP_INT (1 << 11)
+#define NFC_V1_V2_CONFIG2_INT (1 << 15)
+
+#define operation config2
+#define readnfc readw
+#define writenfc writew
#endif /* __FSL_NFC_H */
diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c
index a40c998..615e820 100644
--- a/nand_spl/nand_boot_fsl_nfc.c
+++ b/nand_spl/nand_boot_fsl_nfc.c
@@ -36,13 +36,13 @@ static void nfc_wait_ready(void)
{
uint32_t tmp;
- while (!(readw(&nfc->config2) & NFC_INT))
+ while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT))
;
/* Reset interrupt flag */
- tmp = readw(&nfc->config2);
- tmp &= ~NFC_INT;
- writew(tmp, &nfc->config2);
+ tmp = readnfc(&nfc->config2);
+ tmp &= ~NFC_V1_V2_CONFIG2_INT;
+ writenfc(tmp, &nfc->config2);
}
static void nfc_nand_init(void)
@@ -51,43 +51,45 @@ static void nfc_nand_init(void)
int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
int config1;
- writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
+ writenfc(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
/* unlocking RAM Buff */
- writew(0x2, &nfc->config);
+ writenfc(0x2, &nfc->config);
/* hardware ECC checking and correct */
- config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK |
- NFC_ONE_CYCLE | NFC_FP_INT;
+ config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN |
+ NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE |
+ NFC_V2_CONFIG1_FP_INT;
/*
* if spare size is larger that 16 bytes per 512 byte hunk
* then use 8 symbol correction instead of 4
*/
if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16)
- config1 &= ~NFC_4_8N_ECC;
+ config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4;
else
- config1 |= NFC_4_8N_ECC;
- writew(config1, &nfc->config1);
+ config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
+ writenfc(config1, &nfc->config1);
#elif defined(MXC_NFC_V1)
/* unlocking RAM Buff */
- writew(0x2, &nfc->config);
+ writenfc(0x2, &nfc->config);
/* hardware ECC checking and correct */
- writew(NFC_ECC_EN | NFC_INT_MSK, &nfc->config1);
+ writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK,
+ &nfc->config1);
#endif
}
static void nfc_nand_command(unsigned short command)
{
- writew(command, &nfc->flash_cmd);
- writew(NFC_CMD, &nfc->config2);
+ writenfc(command, &nfc->flash_cmd);
+ writenfc(NFC_CMD, &nfc->operation);
nfc_wait_ready();
}
static void nfc_nand_address(unsigned short address)
{
- writew(address, &nfc->flash_addr);
- writew(NFC_ADDR, &nfc->config2);
+ writenfc(address, &nfc->flash_addr);
+ writenfc(NFC_ADDR, &nfc->operation);
nfc_wait_ready();
}
@@ -121,8 +123,8 @@ static void nfc_nand_data_output(void)
int i;
#endif
- writew(0, &nfc->buf_addr);
- writew(NFC_OUTPUT, &nfc->config2);
+ writenfc(0, &nfc->buf_addr);
+ writenfc(NFC_OUTPUT, &nfc->operation);
nfc_wait_ready();
#ifdef NAND_MXC_2K_MULTI_CYCLE
/*
@@ -130,8 +132,8 @@ static void nfc_nand_data_output(void)
* for pages larger than 512 bytes.
*/
for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) {
- writew(i, &nfc->buf_addr);
- writew(NFC_OUTPUT, &nfc->config2);
+ writenfc(i, &nfc->buf_addr);
+ writenfc(NFC_OUTPUT, &nfc->operation);
nfc_wait_ready();
}
#endif
@@ -160,7 +162,8 @@ static int nfc_nand_check_ecc(void)
static void nfc_nand_read_page(unsigned int page_address)
{
- writew(0, &nfc->buf_addr); /* read in first 0 buffer */
+ /* read in first 0 buffer */
+ writenfc(0, &nfc->buf_addr);
nfc_nand_command(NAND_CMD_READ0);
nfc_nand_page_address(page_address);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v4 2/9] nand: mxc: Add support for i.MX5
2013-02-06 21:37 [U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5 Benoît Thébaudeau
@ 2013-02-06 21:37 ` Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 3/9] imx: mx5: lowlevel_init: Simplify code Benoît Thébaudeau
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Benoît Thébaudeau @ 2013-02-06 21:37 UTC (permalink / raw)
To: u-boot
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
Changes in v4: None
Changes in v3:
- Separate code reformatting from behavioral changes.
Changes in v2: None
arch/arm/include/asm/arch-mx5/imx-regs.h | 9 +++
drivers/mtd/nand/mxc_nand.c | 129 +++++++++++++++++++++++++++---
include/fsl_nfc.h | 79 +++++++++++++++++-
nand_spl/nand_boot_fsl_nfc.c | 67 +++++++++++++++-
4 files changed, 269 insertions(+), 15 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 249d15a..9aa0c6a 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -224,6 +224,15 @@
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
/*
+ * SRC register definitions
+ */
+#if defined(CONFIG_MX51)
+#define SRC_SBMR_NF16B (1 << 2)
+#elif defined(CONFIG_MX53)
+#define SRC_SBMR_NF16B (1 << 13)
+#endif
+
+/*
* CSPI register definitions
*/
#define MXC_ECSPI
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 045df49..cead757 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -22,7 +22,8 @@
#include <nand.h>
#include <linux/err.h>
#include <asm/io.h>
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
+ defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
#include <fsl_nfc.h>
@@ -36,6 +37,9 @@ struct mxc_nand_host {
struct nand_chip *nand;
struct fsl_nfc_regs __iomem *regs;
+#ifdef MXC_NFC_V3_2
+ struct fsl_nfc_ip_regs __iomem *ip_regs;
+#endif
int spare_only;
int status_request;
int pagesize_2k;
@@ -77,7 +81,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = {
.oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
};
#endif
-#elif defined(MXC_NFC_V2_1)
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
#ifndef CONFIG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
@@ -130,6 +134,16 @@ static int is_16bit_nand(void)
else
return 0;
}
+#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
+static int is_16bit_nand(void)
+{
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ if (readl(&src->sbmr) & SRC_SBMR_NF16B)
+ return 1;
+ else
+ return 0;
+}
#else
#warning "8/16 bit NAND autodetection not supported"
static int is_16bit_nand(void)
@@ -158,10 +172,17 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries,
uint32_t tmp;
while (max_retries-- > 0) {
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
tmp = readnfc(&host->regs->config2);
if (tmp & NFC_V1_V2_CONFIG2_INT) {
tmp &= ~NFC_V1_V2_CONFIG2_INT;
writenfc(tmp, &host->regs->config2);
+#elif defined(MXC_NFC_V3_2)
+ tmp = readnfc(&host->ip_regs->ipc);
+ if (tmp & NFC_V3_IPC_INT) {
+ tmp &= ~NFC_V3_IPC_INT;
+ writenfc(tmp, &host->ip_regs->ipc);
+#endif
break;
}
udelay(1);
@@ -213,7 +234,7 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
if (spare_only)
MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
int i;
/*
* The controller copies the 64 bytes of spare data from
@@ -229,11 +250,18 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
}
}
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
writenfc(buf_id, &host->regs->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
+ tmp |= NFC_V3_CONFIG1_RBA(buf_id);
+ writenfc(tmp, &host->regs->config1);
+#endif
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint16_t config1 = readnfc(&host->regs->config1);
+ uint32_t config1 = readnfc(&host->regs->config1);
if (spare_only)
config1 |= NFC_CONFIG1_SP_EN;
else
@@ -256,7 +284,14 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
writenfc(buf_id, &host->regs->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
+ tmp |= NFC_V3_CONFIG1_RBA(buf_id);
+ writenfc(tmp, &host->regs->config1);
+#endif
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
@@ -273,7 +308,7 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
int i;
/*
@@ -293,10 +328,16 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
/* Request the NANDFC to perform a read of the NAND device ID. */
static void send_read_id(struct mxc_nand_host *host)
{
- uint16_t tmp;
+ uint32_t tmp;
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
/* NANDFC buffer 0 is used for device ID output */
writenfc(0x0, &host->regs->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
+ writenfc(tmp, &host->regs->config1);
+#endif
/* Read ID into main buffer */
tmp = readnfc(&host->regs->config1);
@@ -315,15 +356,19 @@ static void send_read_id(struct mxc_nand_host *host)
*/
static uint16_t get_dev_status(struct mxc_nand_host *host)
{
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
void __iomem *main_buf = host->regs->main_area[1];
uint32_t store;
- uint16_t ret, tmp;
+#endif
+ uint32_t ret, tmp;
/* Issue status request to NAND device */
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
/* store the main area1 first word, later do recovery */
store = readl(main_buf);
/* NANDFC buffer 1 is used for device status */
writenfc(1, &host->regs->buf_addr);
+#endif
/* Read status into main buffer */
tmp = readnfc(&host->regs->config1);
@@ -335,12 +380,16 @@ static uint16_t get_dev_status(struct mxc_nand_host *host)
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
/*
* Status is placed in first word of main buffer
* get status, then recovery area 1 data
*/
ret = readw(main_buf);
writel(store, main_buf);
+#elif defined(MXC_NFC_V3_2)
+ ret = readnfc(&host->regs->config1) >> 16;
+#endif
return ret;
}
@@ -359,6 +408,7 @@ static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
uint16_t tmp = readnfc(&host->regs->config1);
if (on)
@@ -366,6 +416,15 @@ static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
else
tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
writenfc(tmp, &host->regs->config1);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(&host->ip_regs->config2);
+
+ if (on)
+ tmp |= NFC_V3_CONFIG2_ECC_EN;
+ else
+ tmp &= ~NFC_V3_CONFIG2_ECC_EN;
+ writenfc(tmp, &host->ip_regs->config2);
+#endif
}
#ifdef CONFIG_MXC_NAND_HWECC
@@ -377,7 +436,7 @@ static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
*/
}
-#ifdef MXC_NFC_V2_1
+#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
int page, int sndcmd)
@@ -1167,8 +1226,8 @@ static struct nand_bbt_descr bbt_mirror_descr = {
int board_nand_init(struct nand_chip *this)
{
struct mtd_info *mtd;
-#ifdef MXC_NFC_V2_1
- uint16_t tmp;
+#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
+ uint32_t tmp;
#endif
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
@@ -1196,13 +1255,17 @@ int board_nand_init(struct nand_chip *this)
this->verify_buf = mxc_nand_verify_buf;
host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+#ifdef MXC_NFC_V3_2
+ host->ip_regs =
+ (struct fsl_nfc_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
+#endif
host->clk_act = 1;
#ifdef CONFIG_MXC_NAND_HWECC
this->ecc.calculate = mxc_nand_calculate_ecc;
this->ecc.hwctl = mxc_nand_enable_hwecc;
this->ecc.correct = mxc_nand_correct_data;
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
this->ecc.mode = NAND_ECC_HW_SYNDROME;
this->ecc.read_page = mxc_nand_read_page_syndrome;
this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
@@ -1240,6 +1303,7 @@ int board_nand_init(struct nand_chip *this)
this->ecc.layout = &nand_hw_eccoob;
#endif
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
#ifdef MXC_NFC_V2_1
tmp = readnfc(&host->regs->config1);
tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
@@ -1274,6 +1338,49 @@ int board_nand_init(struct nand_chip *this)
/* Unlock Block Command for given address range */
writenfc(0x4, &host->regs->wrprot);
+#elif defined(MXC_NFC_V3_2)
+ writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
+ writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
+
+ /* Unlock the internal RAM Buffer */
+ writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
+ &host->ip_regs->wrprot);
+
+ /* Blocks to be unlocked */
+ for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
+ writenfc(0x0 | 0xFFFF << 16,
+ &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
+
+ writenfc(0, &host->ip_regs->ipc);
+
+ tmp = readnfc(&host->ip_regs->config2);
+ tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
+ NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
+ tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
+
+ if (host->pagesize_2k) {
+ tmp |= NFC_V3_CONFIG2_SPAS(64/2);
+ tmp |= NFC_V3_CONFIG2_PS_2048;
+ } else {
+ tmp |= NFC_V3_CONFIG2_SPAS(16/2);
+ tmp |= NFC_V3_CONFIG2_PS_512;
+ }
+
+ writenfc(tmp, &host->ip_regs->config2);
+
+ tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
+ NFC_V3_CONFIG3_NO_SDMA |
+ NFC_V3_CONFIG3_RBB_MODE |
+ NFC_V3_CONFIG3_SBB(6) | /* Reset default */
+ NFC_V3_CONFIG3_ADD_OP(0);
+
+ if (!(this->options & NAND_BUSWIDTH_16))
+ tmp |= NFC_V3_CONFIG3_FW8;
+
+ writenfc(tmp, &host->ip_regs->config3);
+
+ writenfc(0, &host->ip_regs->delay_line);
+#endif
return 0;
}
diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h
index 013e9e2..48a6448 100644
--- a/include/fsl_nfc.h
+++ b/include/fsl_nfc.h
@@ -33,7 +33,8 @@
* to support up to 2K byte pagesize nand.
* Reading or writing a 2K page requires 4 FDI/FDO cycles.
*
- * MX25 and MX35 have version 2.1, which has:
+ * MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which
+ * have:
* 8 512-byte main buffers and
* 8 64-byte spare buffers
* to support up to 4K byte pagesize nand.
@@ -44,20 +45,29 @@
#define MXC_NFC_V1
#define is_mxc_nfc_1() 1
#define is_mxc_nfc_21() 0
+#define is_mxc_nfc_32() 0
#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
#define MXC_NFC_V2_1
#define is_mxc_nfc_1() 0
#define is_mxc_nfc_21() 1
+#define is_mxc_nfc_32() 0
+#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#define MXC_NFC_V3
+#define MXC_NFC_V3_2
+#define is_mxc_nfc_1() 0
+#define is_mxc_nfc_21() 0
+#define is_mxc_nfc_32() 1
#else
#error "MXC NFC implementation not supported"
#endif
+#define is_mxc_nfc_3() is_mxc_nfc_32()
#if defined(MXC_NFC_V1)
#define NAND_MXC_NR_BUFS 4
#define NAND_MXC_SPARE_BUF_SIZE 16
#define NAND_MXC_REG_OFFSET 0xe00
#define NAND_MXC_2K_MULTI_CYCLE
-#elif defined(MXC_NFC_V2_1)
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
#define NAND_MXC_NR_BUFS 8
#define NAND_MXC_SPARE_BUF_SIZE 64
#define NAND_MXC_REG_OFFSET 0x1e00
@@ -110,9 +120,28 @@ struct fsl_nfc_regs {
u16 unlockend_blkaddr2;
u16 unlockstart_blkaddr3;
u16 unlockend_blkaddr3;
+#elif defined(MXC_NFC_V3_2)
+ u32 flash_cmd;
+ u32 flash_addr[12];
+ u32 config1;
+ u32 ecc_status_result;
+ u32 status_sum;
+ u32 launch;
#endif
};
+#ifdef MXC_NFC_V3_2
+struct fsl_nfc_ip_regs {
+ u32 wrprot;
+ u32 wrprot_unlock_blkaddr[8];
+ u32 config2;
+ u32 config3;
+ u32 ipc;
+ u32 err_addr;
+ u32 delay_line;
+};
+#endif
+
/* Set FCMD to 1, rest to 0 for Command operation */
#define NFC_CMD 0x1
@@ -131,20 +160,66 @@ struct fsl_nfc_regs {
/* Set FDO to 100, rest to 0 for Read Status operation */
#define NFC_STATUS 0x20
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
#define NFC_CONFIG1_SP_EN (1 << 2)
#define NFC_CONFIG1_RST (1 << 6)
#define NFC_CONFIG1_CE (1 << 7)
+#elif defined(MXC_NFC_V3_2)
+#define NFC_CONFIG1_SP_EN (1 << 0)
+#define NFC_CONFIG1_CE (1 << 1)
+#define NFC_CONFIG1_RST (1 << 2)
+#endif
#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
#define NFC_V2_CONFIG1_FP_INT (1 << 11)
+#define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4)
+#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4)
#define NFC_V1_V2_CONFIG2_INT (1 << 15)
+#define NFC_V3_CONFIG2_PS_MASK (0x3 << 0)
+#define NFC_V3_CONFIG2_PS_512 (0 << 0)
+#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
+#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
+#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
+#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
+#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
+#define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5)
+#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
+#define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7)
+#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
+#define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9)
+#define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9)
+#define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12)
+#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
+#define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16)
+#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
+#define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24)
+#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
+
+#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
+#define NFC_V3_CONFIG3_FW8 (1 << 3)
+#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
+#define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12)
+#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
+#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
+#define NFC_V3_WRPROT_UNLOCK (1 << 2)
+#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
+
+#define NFC_V3_IPC_CREQ (1 << 0)
+#define NFC_V3_IPC_INT (1 << 31)
+
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
#define operation config2
#define readnfc readw
#define writenfc writew
+#elif defined(MXC_NFC_V3_2)
+#define operation launch
+#define readnfc readl
+#define writenfc writel
+#endif
#endif /* __FSL_NFC_H */
diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c
index 615e820..1096727 100644
--- a/nand_spl/nand_boot_fsl_nfc.c
+++ b/nand_spl/nand_boot_fsl_nfc.c
@@ -30,12 +30,18 @@
#include <asm/io.h>
#include <fsl_nfc.h>
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR;
+#elif defined(MXC_NFC_V3_2)
+static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR_AXI;
+static struct fsl_nfc_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR;
+#endif
static void nfc_wait_ready(void)
{
uint32_t tmp;
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT))
;
@@ -43,11 +49,56 @@ static void nfc_wait_ready(void)
tmp = readnfc(&nfc->config2);
tmp &= ~NFC_V1_V2_CONFIG2_INT;
writenfc(tmp, &nfc->config2);
+#elif defined(MXC_NFC_V3_2)
+ while (!(readnfc(&nfc_ip->ipc) & NFC_V3_IPC_INT))
+ ;
+
+ /* Reset interrupt flag */
+ tmp = readnfc(&nfc_ip->ipc);
+ tmp &= ~NFC_V3_IPC_INT;
+ writenfc(tmp, &nfc_ip->ipc);
+#endif
}
static void nfc_nand_init(void)
{
-#if defined(MXC_NFC_V2_1)
+#if defined(MXC_NFC_V3_2)
+ int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+ int tmp;
+
+ tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK |
+ NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) |
+ NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_SPARE_SIZE / 2) |
+ NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN |
+ NFC_V3_CONFIG2_ONE_CYCLE;
+ if (CONFIG_SYS_NAND_PAGE_SIZE == 4096)
+ tmp |= NFC_V3_CONFIG2_PS_4096;
+ else if (CONFIG_SYS_NAND_PAGE_SIZE == 2048)
+ tmp |= NFC_V3_CONFIG2_PS_2048;
+ else if (CONFIG_SYS_NAND_PAGE_SIZE == 512)
+ tmp |= NFC_V3_CONFIG2_PS_512;
+ /*
+ * if spare size is larger that 16 bytes per 512 byte hunk
+ * then use 8 symbol correction instead of 4
+ */
+ if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16)
+ tmp |= NFC_V3_CONFIG2_ECC_MODE_8;
+ else
+ tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8;
+ writenfc(tmp, &nfc_ip->config2);
+
+ tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
+ NFC_V3_CONFIG3_NO_SDMA |
+ NFC_V3_CONFIG3_RBB_MODE |
+ NFC_V3_CONFIG3_SBB(6) | /* Reset default */
+ NFC_V3_CONFIG3_ADD_OP(0);
+#ifndef CONFIG_SYS_NAND_BUSWIDTH_16
+ tmp |= NFC_V3_CONFIG3_FW8;
+#endif
+ writenfc(tmp, &nfc_ip->config3);
+
+ writenfc(0, &nfc_ip->delay_line);
+#elif defined(MXC_NFC_V2_1)
int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
int config1;
@@ -123,7 +174,13 @@ static void nfc_nand_data_output(void)
int i;
#endif
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
writenfc(0, &nfc->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ int config1 = readnfc(&nfc->config1);
+ config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
+ writenfc(config1, &nfc->config1);
+#endif
writenfc(NFC_OUTPUT, &nfc->operation);
nfc_wait_ready();
#ifdef NAND_MXC_2K_MULTI_CYCLE
@@ -144,7 +201,7 @@ static int nfc_nand_check_ecc(void)
#if defined(MXC_NFC_V1)
u16 ecc_status = readw(&nfc->ecc_status_result);
return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2;
-#elif defined(MXC_NFC_V2_1)
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
u32 ecc_status = readl(&nfc->ecc_status_result);
int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
int err_limit = CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16 ? 8 : 4;
@@ -163,7 +220,13 @@ static int nfc_nand_check_ecc(void)
static void nfc_nand_read_page(unsigned int page_address)
{
/* read in first 0 buffer */
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
writenfc(0, &nfc->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ int config1 = readnfc(&nfc->config1);
+ config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
+ writenfc(config1, &nfc->config1);
+#endif
nfc_nand_command(NAND_CMD_READ0);
nfc_nand_page_address(page_address);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v4 3/9] imx: mx5: lowlevel_init: Simplify code
2013-02-06 21:37 [U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5 Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 2/9] nand: mxc: Add " Benoît Thébaudeau
@ 2013-02-06 21:37 ` Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 4/9] imx: mx53ard: Add support for NAND Flash Benoît Thébaudeau
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Benoît Thébaudeau @ 2013-02-06 21:37 UTC (permalink / raw)
To: u-boot
Don't use several instructions to build constant values.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Acked-by: Stefano Babic <sbabic@denx.de>
---
Changes in v4: None
Changes in v3:
- New patch.
Changes in v2: None
arch/arm/cpu/armv7/mx5/lowlevel_init.S | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 6d9396a..dfce0ca 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -309,8 +309,7 @@ setup_pll_func:
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00015154
str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x02888945
- orr r1, r1, #(1 << 16)
+ ldr r1, =0x02898945
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
@@ -321,10 +320,7 @@ setup_pll_func:
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x00808145
- orr r1, r1, #(2 << 10)
- orr r1, r1, #(0 << 16)
- orr r1, r1, #(1 << 19)
+ ldr r1, =0x00888945
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v4 4/9] imx: mx53ard: Add support for NAND Flash
2013-02-06 21:37 [U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5 Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 2/9] nand: mxc: Add " Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 3/9] imx: mx5: lowlevel_init: Simplify code Benoît Thébaudeau
@ 2013-02-06 21:37 ` Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 5/9] nand: mxc: Fix debug trace in mxc_nand_read_oob_syndrome() Benoît Thébaudeau
` (4 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Benoît Thébaudeau @ 2013-02-06 21:37 UTC (permalink / raw)
To: u-boot
Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB
pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard.
eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this
board, which satisfies the 30-ns NF R/W cycle requirement.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
Changes in v4: None
Changes in v3:
- New patch.
Changes in v2: None
board/freescale/mx53ard/mx53ard.c | 18 ++++++++++++++++++
include/configs/mx53ard.h | 10 ++++++++++
2 files changed, 28 insertions(+)
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index 2fc8570..8907388 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -58,6 +58,23 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
+#ifdef CONFIG_NAND_MXC
+static void setup_iomux_nand(void)
+{
+ mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
+}
+#else
+static void setup_iomux_nand(void)
+{
+}
+#endif
+
static void setup_iomux_uart(void)
{
/* UART1 RXD */
@@ -277,6 +294,7 @@ static void weim_cs1_settings(void)
int board_early_init_f(void)
{
+ setup_iomux_nand();
setup_iomux_uart();
return 0;
}
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 62cb42b..148f7a2 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -41,6 +41,16 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_CMD_NAND
+
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v4 5/9] nand: mxc: Fix debug trace in mxc_nand_read_oob_syndrome()
2013-02-06 21:37 [U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5 Benoît Thébaudeau
` (2 preceding siblings ...)
2013-02-06 21:37 ` [U-Boot] [PATCH v4 4/9] imx: mx53ard: Add support for NAND Flash Benoît Thébaudeau
@ 2013-02-06 21:37 ` Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 6/9] nand: mxc: Use appropriate page number in syndrome functions Benoît Thébaudeau
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Benoît Thébaudeau @ 2013-02-06 21:37 UTC (permalink / raw)
To: u-boot
The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did
not match the page being worked on.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
Changes in v4:
- New patch.
Changes in v3: None
Changes in v2: None
drivers/mtd/nand/mxc_nand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index cead757..6a709c5 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -450,7 +450,7 @@ static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
MTDDEBUG(MTD_DEBUG_LEVEL0,
"%s: Reading OOB area of page %u to oob %p\n",
- __FUNCTION__, host->page_addr, buf);
+ __FUNCTION__, page, buf);
chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
for (i = 0; i < chip->ecc.steps; i++) {
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v4 6/9] nand: mxc: Use appropriate page number in syndrome functions
2013-02-06 21:37 [U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5 Benoît Thébaudeau
` (3 preceding siblings ...)
2013-02-06 21:37 ` [U-Boot] [PATCH v4 5/9] nand: mxc: Fix debug trace in mxc_nand_read_oob_syndrome() Benoît Thébaudeau
@ 2013-02-06 21:37 ` Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 7/9] Makefile: u-boot-with-spl.bin: Pad to CONFIG_SPL_MAX_SIZE Benoît Thébaudeau
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Benoît Thébaudeau @ 2013-02-06 21:37 UTC (permalink / raw)
To: u-boot
The syndrome functions should use the page number passed as argument instead of
the page number saved upon NAND_CMD_READ0.
This does not make any difference if the NAND_NO_AUTOINCR option is set, but
otherwise this fixes accesses to the wrong pages.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
Changes in v4:
- New patch.
Changes in v3: None
Changes in v2: None
drivers/mtd/nand/mxc_nand.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 6a709c5..32240ea 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -504,7 +504,7 @@ static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
int n;
_mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
host->col_addr = n * eccsize;
@@ -548,7 +548,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
uint8_t *oob = chip->oob_poi;
MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
- host->page_addr, buf, oob);
+ page, buf, oob);
/* first read the data area and the available portion of OOB */
for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
@@ -586,7 +586,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
/* Then switch ECC off and read the OOB area to get the ECC code */
_mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
eccsteps = chip->ecc.steps;
oob = chip->oob_poi + chip->ecc.prepad;
for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v4 7/9] Makefile: u-boot-with-spl.bin: Pad to CONFIG_SPL_MAX_SIZE
2013-02-06 21:37 [U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5 Benoît Thébaudeau
` (4 preceding siblings ...)
2013-02-06 21:37 ` [U-Boot] [PATCH v4 6/9] nand: mxc: Use appropriate page number in syndrome functions Benoît Thébaudeau
@ 2013-02-06 21:37 ` Benoît Thébaudeau
2013-02-06 21:38 ` Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 8/9] nand: mxc: Switch NAND SPL to generic SPL Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 9/9] imx: Add u-boot-with-spl.imx make target Benoît Thébaudeau
7 siblings, 1 reply; 10+ messages in thread
From: Benoît Thébaudeau @ 2013-02-06 21:37 UTC (permalink / raw)
To: u-boot
PAD_TO is not a generic SPL configuration option, so use CONFIG_SPL_MAX_SIZE
instead.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
Changes in v4:
- New patch.
Changes in v3: None
Changes in v2: None
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index f4a9b33..d28e608 100644
--- a/Makefile
+++ b/Makefile
@@ -486,7 +486,7 @@ $(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v4 8/9] nand: mxc: Switch NAND SPL to generic SPL
2013-02-06 21:37 [U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5 Benoît Thébaudeau
` (5 preceding siblings ...)
2013-02-06 21:37 ` [U-Boot] [PATCH v4 7/9] Makefile: u-boot-with-spl.bin: Pad to CONFIG_SPL_MAX_SIZE Benoît Thébaudeau
@ 2013-02-06 21:37 ` Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 9/9] imx: Add u-boot-with-spl.imx make target Benoît Thébaudeau
7 siblings, 0 replies; 10+ messages in thread
From: Benoît Thébaudeau @ 2013-02-06 21:37 UTC (permalink / raw)
To: u-boot
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
Changes in v4:
- New patch.
Changes in v3: None
Changes in v2: None
board/freescale/mx31pdk/config.mk | 5 --
.../freescale/mx31pdk/u-boot-spl.lds | 0
board/karo/tx25/config.mk | 5 --
.../u-boot.lds => board/karo/tx25/u-boot-spl.lds | 0
boards.cfg | 2 +-
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/mxc_nand.c | 10 +--
include/fsl_nfc.h => drivers/mtd/nand/mxc_nand.h | 10 +--
.../mtd/nand/mxc_nand_spl.c | 22 ++---
include/configs/mx31pdk.h | 10 ++-
include/configs/tx25.h | 13 ++-
nand_spl/board/freescale/mx31pdk/Makefile | 68 ---------------
nand_spl/board/karo/tx25/Makefile | 89 --------------------
nand_spl/board/karo/tx25/config.mk | 1 -
14 files changed, 41 insertions(+), 195 deletions(-)
delete mode 100644 board/freescale/mx31pdk/config.mk
rename nand_spl/board/freescale/mx31pdk/u-boot.lds => board/freescale/mx31pdk/u-boot-spl.lds (100%)
delete mode 100644 board/karo/tx25/config.mk
rename nand_spl/board/karo/tx25/u-boot.lds => board/karo/tx25/u-boot-spl.lds (100%)
rename include/fsl_nfc.h => drivers/mtd/nand/mxc_nand.h (98%)
rename nand_spl/nand_boot_fsl_nfc.c => drivers/mtd/nand/mxc_nand_spl.c (93%)
delete mode 100644 nand_spl/board/freescale/mx31pdk/Makefile
delete mode 100644 nand_spl/board/karo/tx25/Makefile
delete mode 100644 nand_spl/board/karo/tx25/config.mk
diff --git a/board/freescale/mx31pdk/config.mk b/board/freescale/mx31pdk/config.mk
deleted file mode 100644
index de2c642..0000000
--- a/board/freescale/mx31pdk/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-ifdef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = 0x87ec0000
-else
-CONFIG_SYS_TEXT_BASE = 0x87f00000
-endif
diff --git a/nand_spl/board/freescale/mx31pdk/u-boot.lds b/board/freescale/mx31pdk/u-boot-spl.lds
similarity index 100%
rename from nand_spl/board/freescale/mx31pdk/u-boot.lds
rename to board/freescale/mx31pdk/u-boot-spl.lds
diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk
deleted file mode 100644
index 18b2883..0000000
--- a/board/karo/tx25/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-ifdef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = 0x810c0000
-else
-CONFIG_SYS_TEXT_BASE = 0x81200000
-endif
diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/board/karo/tx25/u-boot-spl.lds
similarity index 100%
rename from nand_spl/board/karo/tx25/u-boot.lds
rename to board/karo/tx25/u-boot-spl.lds
diff --git a/boards.cfg b/boards.cfg
index 7d03620..2649c88 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -45,7 +45,7 @@ imx31_phycore arm arm1136 - -
imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET
qong arm arm1136 - davedenx mx31
mx31ads arm arm1136 - freescale mx31
-mx31pdk arm arm1136 - freescale mx31 mx31pdk:NAND_U_BOOT
+mx31pdk arm arm1136 - freescale mx31
tt01 arm arm1136 - hale mx31
imx31_litekit arm arm1136 - logicpd mx31
flea3 arm arm1136 - CarMediaLab mx35
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index c77c0c4..bcb7161 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -82,6 +82,7 @@ COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
else # minimal SPL drivers
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
+COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
endif # drivers
endif # nand
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 32240ea..7519900 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -26,7 +26,7 @@
defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
-#include <fsl_nfc.h>
+#include "mxc_nand.h"
#define DRIVER_NAME "mxc_nand"
@@ -36,9 +36,9 @@ struct mxc_nand_host {
struct mtd_info mtd;
struct nand_chip *nand;
- struct fsl_nfc_regs __iomem *regs;
+ struct mxc_nand_regs __iomem *regs;
#ifdef MXC_NFC_V3_2
- struct fsl_nfc_ip_regs __iomem *ip_regs;
+ struct mxc_nand_ip_regs __iomem *ip_regs;
#endif
int spare_only;
int status_request;
@@ -1254,10 +1254,10 @@ int board_nand_init(struct nand_chip *this)
this->read_buf = mxc_nand_read_buf;
this->verify_buf = mxc_nand_verify_buf;
- host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+ host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
#ifdef MXC_NFC_V3_2
host->ip_regs =
- (struct fsl_nfc_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
+ (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
#endif
host->clk_act = 1;
diff --git a/include/fsl_nfc.h b/drivers/mtd/nand/mxc_nand.h
similarity index 98%
rename from include/fsl_nfc.h
rename to drivers/mtd/nand/mxc_nand.h
index 48a6448..308ff8d 100644
--- a/include/fsl_nfc.h
+++ b/drivers/mtd/nand/mxc_nand.h
@@ -20,8 +20,8 @@
* MA 02111-1307 USA
*/
-#ifndef __FSL_NFC_H
-#define __FSL_NFC_H
+#ifndef __MXC_NAND_H
+#define __MXC_NAND_H
/*
* Register map and bit definitions for the Freescale NAND Flash Controller
@@ -73,7 +73,7 @@
#define NAND_MXC_REG_OFFSET 0x1e00
#endif
-struct fsl_nfc_regs {
+struct mxc_nand_regs {
u8 main_area[NAND_MXC_NR_BUFS][0x200];
u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
/*
@@ -131,7 +131,7 @@ struct fsl_nfc_regs {
};
#ifdef MXC_NFC_V3_2
-struct fsl_nfc_ip_regs {
+struct mxc_nand_ip_regs {
u32 wrprot;
u32 wrprot_unlock_blkaddr[8];
u32 config2;
@@ -222,4 +222,4 @@ struct fsl_nfc_ip_regs {
#define writenfc writel
#endif
-#endif /* __FSL_NFC_H */
+#endif /* __MXC_NAND_H */
diff --git a/nand_spl/nand_boot_fsl_nfc.c b/drivers/mtd/nand/mxc_nand_spl.c
similarity index 93%
rename from nand_spl/nand_boot_fsl_nfc.c
rename to drivers/mtd/nand/mxc_nand_spl.c
index 1096727..1164dd6 100644
--- a/nand_spl/nand_boot_fsl_nfc.c
+++ b/drivers/mtd/nand/mxc_nand_spl.c
@@ -28,13 +28,13 @@
#include <nand.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
-#include <fsl_nfc.h>
+#include "mxc_nand.h"
#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
-static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR;
+static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR;
#elif defined(MXC_NFC_V3_2)
-static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR_AXI;
-static struct fsl_nfc_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR;
+static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR_AXI;
+static struct mxc_nand_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR;
#endif
static void nfc_wait_ready(void)
@@ -68,7 +68,7 @@ static void nfc_nand_init(void)
tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK |
NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) |
- NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_SPARE_SIZE / 2) |
+ NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_OOBSIZE / 2) |
NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN |
NFC_V3_CONFIG2_ONE_CYCLE;
if (CONFIG_SYS_NAND_PAGE_SIZE == 4096)
@@ -81,7 +81,7 @@ static void nfc_nand_init(void)
* if spare size is larger that 16 bytes per 512 byte hunk
* then use 8 symbol correction instead of 4
*/
- if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16)
+ if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
tmp |= NFC_V3_CONFIG2_ECC_MODE_8;
else
tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8;
@@ -102,7 +102,7 @@ static void nfc_nand_init(void)
int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
int config1;
- writenfc(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
+ writenfc(CONFIG_SYS_NAND_OOBSIZE / 2, &nfc->spare_area_size);
/* unlocking RAM Buff */
writenfc(0x2, &nfc->config);
@@ -115,7 +115,7 @@ static void nfc_nand_init(void)
* if spare size is larger that 16 bytes per 512 byte hunk
* then use 8 symbol correction instead of 4
*/
- if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16)
+ if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4;
else
config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
@@ -204,7 +204,7 @@ static int nfc_nand_check_ecc(void)
#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
u32 ecc_status = readl(&nfc->ecc_status_result);
int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
- int err_limit = CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16 ? 8 : 4;
+ int err_limit = CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16 ? 8 : 4;
int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;
do {
@@ -335,8 +335,8 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
#if defined(CONFIG_ARM)
void board_init_f (ulong bootflag)
{
- relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
- CONFIG_SYS_TEXT_BASE);
+ relocate_code (CONFIG_SPL_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
+ CONFIG_SPL_TEXT_BASE);
}
#endif
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 34e4295..9fee02a 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -45,7 +45,15 @@
#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SPL
+#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE 2048
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SPL_TEXT_BASE 0x87ec0000
+#define CONFIG_SYS_TEXT_BASE 0x87f00000
+
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index 80194d8..23f6ac5 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -31,8 +31,13 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
-/* NAND BOOT is the only boot method */
-#define CONFIG_NAND_U_BOOT
+#define CONFIG_SPL
+#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE 2048
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SPL_TEXT_BASE 0x810c0000
+#define CONFIG_SYS_TEXT_BASE 0x81200000
#ifndef MACH_TYPE_TX25
#define MACH_TYPE_TX25 2177
@@ -40,7 +45,7 @@
#define CONFIG_MACH_TYPE MACH_TYPE_TX25
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
/* Start copying real U-boot from the second page */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
@@ -49,7 +54,7 @@
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_SPARE_SIZE 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024)
diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile
deleted file mode 100644
index fd0dfc1..0000000
--- a/nand_spl/board/freescale/mx31pdk/Makefile
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_NAND_SPL = y
-PAD_TO := 2048
-
-include $(TOPDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-
-SOBJS = start.o crt0.o lowlevel_init.o
-COBJS = nand_boot_fsl_nfc.o
-
-SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
-SRCS += $(SRCTREE)/arch/arm/cpu/arm1136/start.S
-SRCS += $(SRCTREE)/arch/arm/lib/crt0.S
-SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $@
-
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-#########################################################################
-
-$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm1136/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/nand_spl/%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/nand_spl/board/karo/tx25/Makefile b/nand_spl/board/karo/tx25/Makefile
deleted file mode 100644
index 82489d2..0000000
--- a/nand_spl/board/karo/tx25/Makefile
+++ /dev/null
@@ -1,89 +0,0 @@
-#
-# (C) Copyright 2009 DENX Software Engineering
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundatio; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-CONFIG_NAND_SPL = y
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-
-SOBJS = start.o crt0.o lowlevel_init.o
-COBJS = nand_boot_fsl_nfc.o
-
-SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
-SRCS += $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S
-SRCS += $(SRCTREE)/arch/arm/lib/crt0.S
-SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $@
-
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-#########################################################################
-
-$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm926ejs/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/nand_spl/%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/nand_spl/board/karo/tx25/config.mk b/nand_spl/board/karo/tx25/config.mk
deleted file mode 100644
index 68afbf1..0000000
--- a/nand_spl/board/karo/tx25/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-PAD_TO := 2048
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v4 9/9] imx: Add u-boot-with-spl.imx make target
2013-02-06 21:37 [U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5 Benoît Thébaudeau
` (6 preceding siblings ...)
2013-02-06 21:37 ` [U-Boot] [PATCH v4 8/9] nand: mxc: Switch NAND SPL to generic SPL Benoît Thébaudeau
@ 2013-02-06 21:37 ` Benoît Thébaudeau
7 siblings, 0 replies; 10+ messages in thread
From: Benoît Thébaudeau @ 2013-02-06 21:37 UTC (permalink / raw)
To: u-boot
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
Changes in v4:
- New patch.
Changes in v3: None
Changes in v2: None
Makefile | 3 +++
arch/arm/imx-common/Makefile | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/Makefile b/Makefile
index d28e608..d542725 100644
--- a/Makefile
+++ b/Makefile
@@ -470,6 +470,9 @@ $(obj)u-boot.img: $(obj)u-boot.bin
$(OBJTREE)/u-boot.imx : $(obj)u-boot.bin $(SUBDIR_TOOLS) depend
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
+$(OBJTREE)/u-boot-with-spl.imx : $(obj)u-boot-with-spl.bin $(SUBDIR_TOOLS) depend
+ $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
+
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 6309fcd..f27a5f7 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -50,6 +50,10 @@ $(OBJTREE)/u-boot.imx: $(OBJTREE)/u-boot.bin $(OBJTREE)/$(patsubst "%",%,$(CONFI
$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/u-boot-with-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
+ $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
+ -e $(CONFIG_SPL_TEXT_BASE) -d $< $@
+
$(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2013-02-06 21:38 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-02-06 21:37 [U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5 Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 2/9] nand: mxc: Add " Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 3/9] imx: mx5: lowlevel_init: Simplify code Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 4/9] imx: mx53ard: Add support for NAND Flash Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 5/9] nand: mxc: Fix debug trace in mxc_nand_read_oob_syndrome() Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 6/9] nand: mxc: Use appropriate page number in syndrome functions Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 7/9] Makefile: u-boot-with-spl.bin: Pad to CONFIG_SPL_MAX_SIZE Benoît Thébaudeau
2013-02-06 21:38 ` Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 8/9] nand: mxc: Switch NAND SPL to generic SPL Benoît Thébaudeau
2013-02-06 21:37 ` [U-Boot] [PATCH v4 9/9] imx: Add u-boot-with-spl.imx make target Benoît Thébaudeau
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