From: dillon.minfei at gmail.com <dillon.minfei@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH v2 1/6] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts
Date: Fri, 26 Mar 2021 18:24:22 +0800 [thread overview]
Message-ID: <1616754267-13845-2-git-send-email-dillon.minfei@gmail.com> (raw)
In-Reply-To: <1616754267-13845-1-git-send-email-dillon.minfei@gmail.com>
From: dillon min <dillon.minfei@gmail.com>
As different boards has their own sdram hw connection, mount different
sdram modules, so move sdram timing parameter and pin configuration
to their board device tree.
Signed-off-by: dillon min <dillon.minfei@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
v2: add 'pinctrl0 = &pinctrl;' for configure fmc pins (after move gpio(a..k)
register defines to stm32h743.dtsi, need add this)
arch/arm/dts/stm32h7-u-boot.dtsi | 100 ++----------------------------
arch/arm/dts/stm32h743i-disco-u-boot.dtsi | 98 +++++++++++++++++++++++++++++
arch/arm/dts/stm32h743i-eval-u-boot.dtsi | 98 +++++++++++++++++++++++++++++
3 files changed, 201 insertions(+), 95 deletions(-)
diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index 54dd406..84dc765 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -20,6 +20,7 @@
gpio9 = &gpioj;
gpio10 = &gpiok;
mmc0 = &sdmmc1;
+ pinctrl0 = &pinctrl;
};
soc {
@@ -36,30 +37,6 @@
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
status = "okay";
-
- /*
- * Memory configuration from sdram datasheet IS42S32800G-6BLI
- * first bank is bank at 0
- * second bank is bank at 1
- */
- bank1: bank at 1 {
- st,sdram-control = /bits/ 8 <NO_COL_9
- NO_ROW_12
- MWIDTH_32
- BANKS_4
- CAS_2
- SDCLK_3
- RD_BURST_EN
- RD_PIPE_DL_0>;
- st,sdram-timing = /bits/ 8 <TMRD_1
- TXSR_1
- TRAS_1
- TRC_6
- TRP_2
- TWR_1
- TRCD_1>;
- st,sdram-refcount = <1539>;
- };
};
};
};
@@ -136,77 +113,6 @@
compatible = "st,stm32-gpio";
};
-&pinctrl {
- fmc_pins: fmc at 0 {
- pins {
- pinmux = <STM32_PINMUX('D', 0, AF12)>,
- <STM32_PINMUX('D', 1, AF12)>,
- <STM32_PINMUX('D', 8, AF12)>,
- <STM32_PINMUX('D', 9, AF12)>,
- <STM32_PINMUX('D',10, AF12)>,
- <STM32_PINMUX('D',14, AF12)>,
- <STM32_PINMUX('D',15, AF12)>,
-
- <STM32_PINMUX('E', 0, AF12)>,
- <STM32_PINMUX('E', 1, AF12)>,
- <STM32_PINMUX('E', 7, AF12)>,
- <STM32_PINMUX('E', 8, AF12)>,
- <STM32_PINMUX('E', 9, AF12)>,
- <STM32_PINMUX('E',10, AF12)>,
- <STM32_PINMUX('E',11, AF12)>,
- <STM32_PINMUX('E',12, AF12)>,
- <STM32_PINMUX('E',13, AF12)>,
- <STM32_PINMUX('E',14, AF12)>,
- <STM32_PINMUX('E',15, AF12)>,
-
- <STM32_PINMUX('F', 0, AF12)>,
- <STM32_PINMUX('F', 1, AF12)>,
- <STM32_PINMUX('F', 2, AF12)>,
- <STM32_PINMUX('F', 3, AF12)>,
- <STM32_PINMUX('F', 4, AF12)>,
- <STM32_PINMUX('F', 5, AF12)>,
- <STM32_PINMUX('F',11, AF12)>,
- <STM32_PINMUX('F',12, AF12)>,
- <STM32_PINMUX('F',13, AF12)>,
- <STM32_PINMUX('F',14, AF12)>,
- <STM32_PINMUX('F',15, AF12)>,
-
- <STM32_PINMUX('G', 0, AF12)>,
- <STM32_PINMUX('G', 1, AF12)>,
- <STM32_PINMUX('G', 2, AF12)>,
- <STM32_PINMUX('G', 4, AF12)>,
- <STM32_PINMUX('G', 5, AF12)>,
- <STM32_PINMUX('G', 8, AF12)>,
- <STM32_PINMUX('G',15, AF12)>,
-
- <STM32_PINMUX('H', 5, AF12)>,
- <STM32_PINMUX('H', 6, AF12)>,
- <STM32_PINMUX('H', 7, AF12)>,
- <STM32_PINMUX('H', 8, AF12)>,
- <STM32_PINMUX('H', 9, AF12)>,
- <STM32_PINMUX('H',10, AF12)>,
- <STM32_PINMUX('H',11, AF12)>,
- <STM32_PINMUX('H',12, AF12)>,
- <STM32_PINMUX('H',13, AF12)>,
- <STM32_PINMUX('H',14, AF12)>,
- <STM32_PINMUX('H',15, AF12)>,
-
- <STM32_PINMUX('I', 0, AF12)>,
- <STM32_PINMUX('I', 1, AF12)>,
- <STM32_PINMUX('I', 2, AF12)>,
- <STM32_PINMUX('I', 3, AF12)>,
- <STM32_PINMUX('I', 4, AF12)>,
- <STM32_PINMUX('I', 5, AF12)>,
- <STM32_PINMUX('I', 6, AF12)>,
- <STM32_PINMUX('I', 7, AF12)>,
- <STM32_PINMUX('I', 9, AF12)>,
- <STM32_PINMUX('I',10, AF12)>;
-
- slew-rate = <3>;
- };
- };
-};
-
&pwrcfg {
u-boot,dm-pre-reloc;
};
@@ -222,3 +128,7 @@
&timer5 {
u-boot,dm-pre-reloc;
};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
index 5965afc..02e28c6 100644
--- a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
@@ -1,3 +1,101 @@
// SPDX-License-Identifier: GPL-2.0+
#include <stm32h7-u-boot.dtsi>
+
+&fmc {
+
+ /*
+ * Memory configuration from sdram datasheet IS42S32800G-6BLI
+ * first bank is bank at 0
+ * second bank is bank at 1
+ */
+ bank1: bank at 1 {
+ st,sdram-control = /bits/ 8 <NO_COL_9
+ NO_ROW_12
+ MWIDTH_32
+ BANKS_4
+ CAS_2
+ SDCLK_3
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1
+ TXSR_1
+ TRAS_1
+ TRC_6
+ TRP_2
+ TWR_1
+ TRCD_1>;
+ st,sdram-refcount = <1539>;
+ };
+};
+
+&pinctrl {
+ fmc_pins: fmc at 0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, AF12)>,
+ <STM32_PINMUX('D', 1, AF12)>,
+ <STM32_PINMUX('D', 8, AF12)>,
+ <STM32_PINMUX('D', 9, AF12)>,
+ <STM32_PINMUX('D',10, AF12)>,
+ <STM32_PINMUX('D',14, AF12)>,
+ <STM32_PINMUX('D',15, AF12)>,
+
+ <STM32_PINMUX('E', 0, AF12)>,
+ <STM32_PINMUX('E', 1, AF12)>,
+ <STM32_PINMUX('E', 7, AF12)>,
+ <STM32_PINMUX('E', 8, AF12)>,
+ <STM32_PINMUX('E', 9, AF12)>,
+ <STM32_PINMUX('E',10, AF12)>,
+ <STM32_PINMUX('E',11, AF12)>,
+ <STM32_PINMUX('E',12, AF12)>,
+ <STM32_PINMUX('E',13, AF12)>,
+ <STM32_PINMUX('E',14, AF12)>,
+ <STM32_PINMUX('E',15, AF12)>,
+
+ <STM32_PINMUX('F', 0, AF12)>,
+ <STM32_PINMUX('F', 1, AF12)>,
+ <STM32_PINMUX('F', 2, AF12)>,
+ <STM32_PINMUX('F', 3, AF12)>,
+ <STM32_PINMUX('F', 4, AF12)>,
+ <STM32_PINMUX('F', 5, AF12)>,
+ <STM32_PINMUX('F',11, AF12)>,
+ <STM32_PINMUX('F',12, AF12)>,
+ <STM32_PINMUX('F',13, AF12)>,
+ <STM32_PINMUX('F',14, AF12)>,
+ <STM32_PINMUX('F',15, AF12)>,
+
+ <STM32_PINMUX('G', 0, AF12)>,
+ <STM32_PINMUX('G', 1, AF12)>,
+ <STM32_PINMUX('G', 2, AF12)>,
+ <STM32_PINMUX('G', 4, AF12)>,
+ <STM32_PINMUX('G', 5, AF12)>,
+ <STM32_PINMUX('G', 8, AF12)>,
+ <STM32_PINMUX('G',15, AF12)>,
+
+ <STM32_PINMUX('H', 5, AF12)>,
+ <STM32_PINMUX('H', 6, AF12)>,
+ <STM32_PINMUX('H', 7, AF12)>,
+ <STM32_PINMUX('H', 8, AF12)>,
+ <STM32_PINMUX('H', 9, AF12)>,
+ <STM32_PINMUX('H',10, AF12)>,
+ <STM32_PINMUX('H',11, AF12)>,
+ <STM32_PINMUX('H',12, AF12)>,
+ <STM32_PINMUX('H',13, AF12)>,
+ <STM32_PINMUX('H',14, AF12)>,
+ <STM32_PINMUX('H',15, AF12)>,
+
+ <STM32_PINMUX('I', 0, AF12)>,
+ <STM32_PINMUX('I', 1, AF12)>,
+ <STM32_PINMUX('I', 2, AF12)>,
+ <STM32_PINMUX('I', 3, AF12)>,
+ <STM32_PINMUX('I', 4, AF12)>,
+ <STM32_PINMUX('I', 5, AF12)>,
+ <STM32_PINMUX('I', 6, AF12)>,
+ <STM32_PINMUX('I', 7, AF12)>,
+ <STM32_PINMUX('I', 9, AF12)>,
+ <STM32_PINMUX('I',10, AF12)>;
+
+ slew-rate = <3>;
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
index 5965afc..02e28c6 100644
--- a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
+++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
@@ -1,3 +1,101 @@
// SPDX-License-Identifier: GPL-2.0+
#include <stm32h7-u-boot.dtsi>
+
+&fmc {
+
+ /*
+ * Memory configuration from sdram datasheet IS42S32800G-6BLI
+ * first bank is bank at 0
+ * second bank is bank at 1
+ */
+ bank1: bank at 1 {
+ st,sdram-control = /bits/ 8 <NO_COL_9
+ NO_ROW_12
+ MWIDTH_32
+ BANKS_4
+ CAS_2
+ SDCLK_3
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1
+ TXSR_1
+ TRAS_1
+ TRC_6
+ TRP_2
+ TWR_1
+ TRCD_1>;
+ st,sdram-refcount = <1539>;
+ };
+};
+
+&pinctrl {
+ fmc_pins: fmc at 0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, AF12)>,
+ <STM32_PINMUX('D', 1, AF12)>,
+ <STM32_PINMUX('D', 8, AF12)>,
+ <STM32_PINMUX('D', 9, AF12)>,
+ <STM32_PINMUX('D',10, AF12)>,
+ <STM32_PINMUX('D',14, AF12)>,
+ <STM32_PINMUX('D',15, AF12)>,
+
+ <STM32_PINMUX('E', 0, AF12)>,
+ <STM32_PINMUX('E', 1, AF12)>,
+ <STM32_PINMUX('E', 7, AF12)>,
+ <STM32_PINMUX('E', 8, AF12)>,
+ <STM32_PINMUX('E', 9, AF12)>,
+ <STM32_PINMUX('E',10, AF12)>,
+ <STM32_PINMUX('E',11, AF12)>,
+ <STM32_PINMUX('E',12, AF12)>,
+ <STM32_PINMUX('E',13, AF12)>,
+ <STM32_PINMUX('E',14, AF12)>,
+ <STM32_PINMUX('E',15, AF12)>,
+
+ <STM32_PINMUX('F', 0, AF12)>,
+ <STM32_PINMUX('F', 1, AF12)>,
+ <STM32_PINMUX('F', 2, AF12)>,
+ <STM32_PINMUX('F', 3, AF12)>,
+ <STM32_PINMUX('F', 4, AF12)>,
+ <STM32_PINMUX('F', 5, AF12)>,
+ <STM32_PINMUX('F',11, AF12)>,
+ <STM32_PINMUX('F',12, AF12)>,
+ <STM32_PINMUX('F',13, AF12)>,
+ <STM32_PINMUX('F',14, AF12)>,
+ <STM32_PINMUX('F',15, AF12)>,
+
+ <STM32_PINMUX('G', 0, AF12)>,
+ <STM32_PINMUX('G', 1, AF12)>,
+ <STM32_PINMUX('G', 2, AF12)>,
+ <STM32_PINMUX('G', 4, AF12)>,
+ <STM32_PINMUX('G', 5, AF12)>,
+ <STM32_PINMUX('G', 8, AF12)>,
+ <STM32_PINMUX('G',15, AF12)>,
+
+ <STM32_PINMUX('H', 5, AF12)>,
+ <STM32_PINMUX('H', 6, AF12)>,
+ <STM32_PINMUX('H', 7, AF12)>,
+ <STM32_PINMUX('H', 8, AF12)>,
+ <STM32_PINMUX('H', 9, AF12)>,
+ <STM32_PINMUX('H',10, AF12)>,
+ <STM32_PINMUX('H',11, AF12)>,
+ <STM32_PINMUX('H',12, AF12)>,
+ <STM32_PINMUX('H',13, AF12)>,
+ <STM32_PINMUX('H',14, AF12)>,
+ <STM32_PINMUX('H',15, AF12)>,
+
+ <STM32_PINMUX('I', 0, AF12)>,
+ <STM32_PINMUX('I', 1, AF12)>,
+ <STM32_PINMUX('I', 2, AF12)>,
+ <STM32_PINMUX('I', 3, AF12)>,
+ <STM32_PINMUX('I', 4, AF12)>,
+ <STM32_PINMUX('I', 5, AF12)>,
+ <STM32_PINMUX('I', 6, AF12)>,
+ <STM32_PINMUX('I', 7, AF12)>,
+ <STM32_PINMUX('I', 9, AF12)>,
+ <STM32_PINMUX('I',10, AF12)>;
+
+ slew-rate = <3>;
+ };
+ };
+};
--
2.7.4
next prev parent reply other threads:[~2021-03-26 10:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 10:24 [PATCH v2 0/6] Add rt-thread art-pi board support dillon.minfei at gmail.com
2021-03-26 10:24 ` dillon.minfei at gmail.com [this message]
2021-03-26 10:24 ` [PATCH v2 2/6] ARM: dts: stm32: Add RT-Thread " dillon.minfei at gmail.com
2021-03-26 14:24 ` Patrice CHOTARD
2021-03-27 5:10 ` dillon min
2021-03-26 10:24 ` [PATCH v2 3/6] board: Add rt-thread " dillon.minfei at gmail.com
2021-03-26 10:24 ` [PATCH v2 4/6] ram: stm32: fix strsep failed on read only memory dillon.minfei at gmail.com
2021-03-26 10:24 ` [PATCH v2 5/6] dt-bindings: pinctrl: stm32: Add st, stm32h750-pinctrl for stm32h750 soc dillon.minfei at gmail.com
2021-03-26 10:24 ` [PATCH v2 6/6] pinctrl: stm32: Add st, stm32h750-pinctrl compatible string dillon.minfei at gmail.com
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