From: Andre Przywara <andre.przywara@arm.com>
To: Richard Genoud <richard.genoud@bootlin.com>,
Jagan Teki <jagan@amarulasolutions.com>,
Tom Rini <trini@konsulko.com>,
Hans de Goede <hdegoede@redhat.com>,
Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>,
Dario Binacchi <dario.binacchi@amarulasolutions.com>,
Michael Trimarchi <michael@amarulasolutions.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>,
Chen-Yu Tsai <wens@csie.org>,
Andrey Skvortsov <andrej.skvortzov@gmail.com>,
Marek Vasut <marek.vasut+renesas@mailbox.org>,
Anand Gore <anand.gore@broadcom.com>,
Linus Walleij <linus.walleij@linaro.org>,
david regan <dregan@broadcom.com>,
Andrew Goodbody <andrew.goodbody@linaro.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
u-boot@lists.denx.de
Subject: Re: [PATCH 10/24] mtd: rawnand: sunxi: cosmetic: move ECC_PAT_FOUND register in SoC caps
Date: Sat, 18 Oct 2025 00:11:10 +0100 [thread overview]
Message-ID: <16241b87-7589-40ff-9280-cbacf32dc227@arm.com> (raw)
In-Reply-To: <20251016142752.2627710-11-richard.genoud@bootlin.com>
Hi,
On 16/10/2025 15:27, Richard Genoud wrote:
> Move ECC_PAT_FOUND register in SoC capabilities structure
>
> This register offset moved in H616, it's now its own register, not
> shared with NFC_ECC_ST.
> Push that specificity in caps structure.
Right, so if I understand correctly, this moves from bits[31:16] of
ECC_ST to bits[31:0] of a new separate register.
If this is correct, can you add this piece of information to the commit
message, to motivate the addition of the whole field masking operation?
Assuming that this looks alright to me:
> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
> drivers/mtd/nand/raw/sunxi_nand.c | 9 +++++++--
> drivers/mtd/nand/raw/sunxi_nand.h | 16 +++++++++++++++-
> 2 files changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c
> index 64a0db37f3f0..869b3ddd971c 100644
> --- a/drivers/mtd/nand/raw/sunxi_nand.c
> +++ b/drivers/mtd/nand/raw/sunxi_nand.c
> @@ -699,6 +699,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
> struct nand_ecc_ctrl *ecc = &nand->ecc;
> int raw_mode = 0;
> u32 status;
> + u32 pattern_found;
> int ret;
>
> if (*cur_off != data_off)
> @@ -724,8 +725,9 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
>
> *cur_off = oob_off + ecc->bytes + 4;
>
> - status = readl(nfc->regs + NFC_REG_ECC_ST);
> - if (status & NFC_ECC_PAT_FOUND(0)) {
> + pattern_found = readl(nfc->regs + nfc->caps->reg_pat_found);
> + pattern_found = field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found);
> + if (pattern_found & NFC_ECC_PAT_FOUND(0)) {
> u8 pattern = 0xff;
>
> if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1)))
> @@ -744,6 +746,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
> nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
> sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4, true, page);
>
> + status = readl(nfc->regs + NFC_REG_ECC_ST);
> if (status & NFC_ECC_ERR(0)) {
> /*
> * Re-read the data with the randomizer disabled to identify
> @@ -1715,6 +1718,8 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
> .nstrengths = 9,
> .reg_ecc_err_cnt = NFC_REG_A10_ECC_ERR_CNT,
> .reg_user_data = NFC_REG_A10_USER_DATA,
> + .reg_pat_found = NFC_REG_ECC_ST,
> + .pat_found_mask = GENMASK(31, 16),
> };
>
> static const struct udevice_id sunxi_nand_ids[] = {
> diff --git a/drivers/mtd/nand/raw/sunxi_nand.h b/drivers/mtd/nand/raw/sunxi_nand.h
> index 1977d1bd8eaf..35079d37bb1f 100644
> --- a/drivers/mtd/nand/raw/sunxi_nand.h
> +++ b/drivers/mtd/nand/raw/sunxi_nand.h
> @@ -25,6 +25,9 @@
>
> #include <linux/bitops.h>
>
> +/* non compile-time field get */
> +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
> +
> #define NFC_REG_CTL 0x0000
> #define NFC_REG_ST 0x0004
> #define NFC_REG_INT 0x0008
> @@ -146,7 +149,14 @@
>
> /* define bit use in NFC_ECC_ST */
> #define NFC_ECC_ERR(x) BIT(x)
> -#define NFC_ECC_PAT_FOUND(x) BIT((x) + 16)
> +
> +/*
> + * define bit use in NFC_REG_PAT_FOUND
> + * For A10/A23, NFC_REG_PAT_FOUND == NFC_ECC_ST register
> + */
> +#define NFC_ECC_PAT_FOUND(x) BIT(x)
> +#define NFC_ECC_PAT_FOUND_MSK(nfc) ((nfc)->caps->pat_found_mask)
> +
> #define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff)
>
> #define NFC_DEFAULT_TIMEOUT_MS 1000
> @@ -162,11 +172,15 @@
> * @nstrengths: Number of element of ECC strengths array
> * @reg_ecc_err_cnt: ECC error counter register
> * @reg_user_data: User data register
> + * @reg_pat_found: Data Pattern Status Register
> + * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register
> */
> struct sunxi_nfc_caps {
> unsigned int nstrengths;
> unsigned int reg_ecc_err_cnt;
> unsigned int reg_user_data;
> + unsigned int reg_pat_found;
> + unsigned int pat_found_mask;
> };
>
> #endif
next prev parent reply other threads:[~2025-10-17 23:11 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-16 14:27 [PATCH 00/24] Introduce Allwinner H6/H616 NAND controller support Richard Genoud
2025-10-16 14:27 ` [PATCH 01/24] mtd: rawnand: sunxi: cosmetic: remove needless comment Richard Genoud
2025-10-17 7:56 ` Andre Przywara
2025-10-16 14:27 ` [PATCH 02/24] mtd: rawnand: sunxi_spl: fix pointer from integer without a cast Richard Genoud
2025-10-17 7:57 ` Andre Przywara
2025-10-17 12:48 ` Richard GENOUD
2025-10-16 14:27 ` [PATCH 03/24] mtd: rawnand: sunxi_spl: cosmetic: harmonize register defines with non spl file Richard Genoud
2025-10-17 7:57 ` Andre Przywara
2025-10-17 14:22 ` Richard GENOUD
2025-10-17 14:27 ` Andre Przywara
2025-10-16 14:27 ` [PATCH 04/24] mtd: rawnand: sunxi_spl: cosmetic: use definitions from linux/mtd/rawnand.h Richard Genoud
2025-10-17 9:35 ` Andre Przywara
2025-10-16 14:27 ` [PATCH 05/24] mtd: rawnand: sunxi_spl: cosmetic: replace AHB_DIV_1 by CCM_NAND_CTRL_M/N Richard Genoud
2025-10-17 9:36 ` Andre Przywara
2025-10-17 14:26 ` Richard GENOUD
2025-10-16 14:27 ` [PATCH 06/24] mtd: rawnand: sunxi: cosmetic: merge register definitions for sunxi_nand{, _spl}.c Richard Genoud
2025-10-17 23:09 ` [PATCH 06/24] mtd: rawnand: sunxi: cosmetic: merge register definitions for sunxi_nand{,_spl}.c Andre Przywara
2025-10-16 14:27 ` [PATCH 07/24] mtd: rawnand: sunxi: cosmetic: add per SoC capabilities Richard Genoud
2025-10-17 23:10 ` Andre Przywara
2025-10-16 14:27 ` [PATCH 08/24] mtd: rawnand: sunxi: cosmetic: move ECC_ERR_CNT register offset in SoC caps Richard Genoud
2025-10-17 23:10 ` Andre Przywara
2025-10-16 14:27 ` [PATCH 09/24] mtd: rawnand: sunxi: cosmetic: move USER_DATA " Richard Genoud
2025-10-17 23:10 ` Andre Przywara
2025-10-16 14:27 ` [PATCH 10/24] mtd: rawnand: sunxi: cosmetic: move ECC_PAT_FOUND register " Richard Genoud
2025-10-17 23:11 ` Andre Przywara [this message]
2025-10-20 6:46 ` Richard GENOUD
2025-10-16 14:27 ` [PATCH 11/24] mtd: rawnand: sunxi: cosmetic: add has_ecc_block_512 capability Richard Genoud
2025-10-17 23:11 ` Andre Przywara
2025-10-20 7:02 ` Richard GENOUD
2025-10-16 14:27 ` [PATCH 12/24] mtd: rawnand: sunxi: cosmetic: move NFC_ECC_MODE offset in SoC caps Richard Genoud
2025-10-16 14:27 ` [PATCH 13/24] mtd: rawnand: sunxi: cosmetic: introduce reg_pat_id in sunxi_nfc_caps Richard Genoud
2025-10-16 14:27 ` [PATCH 14/24] mtd: rawnand: sunxi_spl: cosmetic: add per SoC capabilities Richard Genoud
2025-10-16 14:27 ` [PATCH 15/24] mtd: rawnand: sunxi: cosmetic: move NFC_RANDOM_EN register offset in SoC caps Richard Genoud
2025-10-16 14:27 ` [PATCH 16/24] mtd: rawnand: sunxi: cosmetic: introduce reg_spare_area in sunxi_nfc_caps Richard Genoud
2025-10-16 14:27 ` [PATCH 17/24] mtd: rawnand: sunxi_spl: use NFC_ECC_ERR_MSK and NFC_ECC_PAT_FOUND Richard Genoud
2025-10-16 14:27 ` [PATCH 18/24] mtd: rawnand: sunxi_spl: increase max_oobsize for 2KiB pages Richard Genoud
2025-10-16 14:27 ` [PATCH 19/24] mtd: rawnand: sunxi_spl: cosmetic: use NFC_ECC_MODE and NFC_RANDOM_SEED macros Richard Genoud
2025-10-16 14:27 ` [PATCH 20/24] sunxi: clock: H6: add NAND controller clock registers Richard Genoud
2025-10-16 14:27 ` [PATCH 21/24] clk: sunxi: Add MBUS Master Clock Gating Register Richard Genoud
2025-10-16 14:27 ` [PATCH 22/24] mtd: rawnand: sunxi: add support for H6/H616 nand controller Richard Genoud
2025-10-20 14:05 ` Richard GENOUD
2025-10-16 14:27 ` [PATCH 23/24] mtd: rawnand: sunxi_spl: " Richard Genoud
2025-10-16 14:27 ` [PATCH 24/24] mtd: rawnand: sunxi_spl: Fix cast to pointer from integer warnings Richard Genoud
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