Re: [PATCH v2 09/15] crypto/fsl: i.MX8: Enable Job ring driver model in SPL and U-Boot.

[Ye Li <ye.li@nxp.com>]

On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX8(QM/QXP) - added support for JR driver model.
> sec is initialized based on job ring information processed
> from device tree.
> 
> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> Signed-off-by: Horia Geantă <horia.geanta@nxp.com>

Reviewed-by: Ye Li <ye.li@nxp.com>

Best regards,
Ye Li

> ---
>  arch/arm/Kconfig                          |  3 +++
>  arch/arm/include/asm/arch-imx8/imx-regs.h |  5 ++++-
>  arch/arm/mach-imx/cmd_dek.c               |  1 +
>  arch/arm/mach-imx/imx8/Kconfig            |  9 +++++++++
>  arch/arm/mach-imx/imx8/cpu.c              | 16 ++++++++++++++-
>  board/freescale/imx8qm_mek/spl.c          |  6 ++++--
>  board/freescale/imx8qxp_mek/spl.c         |  6 ++++--
>  drivers/crypto/fsl/Kconfig                |  2 +-
>  drivers/crypto/fsl/jr.c                   | 24
> +++++++++++++++++++++++
>  include/fsl_sec.h                         | 12 +++++-------
>  10 files changed, 70 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index b3d11c1a0d..982b285e39 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -785,6 +785,9 @@ config ARCH_LPC32XX
>  config ARCH_IMX8
>  	bool "NXP i.MX8 platform"
>  	select ARM64
> +	select SYS_FSL_HAS_SEC
> +	select SYS_FSL_SEC_COMPAT_4
> +	select SYS_FSL_SEC_LE
>  	select DM
>  	select GPIO_EXTRA_HEADER
>  	select OF_CONTROL
> diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h
> b/arch/arm/include/asm/arch-imx8/imx-regs.h
> index ed6e05e556..2d64b0604b 100644
> --- a/arch/arm/include/asm/arch-imx8/imx-regs.h
> +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
> @@ -1,6 +1,6 @@
>  /* SPDX-License-Identifier: GPL-2.0+ */
>  /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
>   */
>  
>  #ifndef __ASM_ARCH_IMX8_REGS_H__
> @@ -47,4 +47,7 @@
>  #define USB_BASE_ADDR		0x5b0d0000
>  #define USB_PHY0_BASE_ADDR	0x5b100000
>  
> +#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
> +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
> +
>  #endif /* __ASM_ARCH_IMX8_REGS_H__ */
> diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-
> imx/cmd_dek.c
> index 89da89c51d..04c4b20a84 100644
> --- a/arch/arm/mach-imx/cmd_dek.c
> +++ b/arch/arm/mach-imx/cmd_dek.c
> @@ -9,6 +9,7 @@
>  #include <command.h>
>  #include <log.h>
>  #include <malloc.h>
> +#include <memalign.h>
>  #include <asm/byteorder.h>
>  #include <linux/compiler.h>
>  #include <fsl_sec.h>
> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-
> imx/imx8/Kconfig
> index b43739e5c6..9a20ebe84e 100644
> --- a/arch/arm/mach-imx/imx8/Kconfig
> +++ b/arch/arm/mach-imx/imx8/Kconfig
> @@ -8,6 +8,7 @@ config AHAB_BOOT
>  
>  config IMX8
>  	bool
> +	select HAS_CAAM
>  
>  config MU_BASE_SPL
>  	hex "MU base address used in SPL"
> @@ -72,6 +73,10 @@ config TARGET_IMX8QM_MEK
>  	bool "Support i.MX8QM MEK board"
>  	select BOARD_LATE_INIT
>  	select IMX8QM
> +	select FSL_CAAM
> +	select FSL_BLOB
> +	select ARCH_MISC_INIT
> +	select SPL_CRYPTO if SPL
>  
>  config TARGET_CONGA_QMX8
>  	bool "Support congatec conga-QMX8 board"
> @@ -89,6 +94,10 @@ config TARGET_IMX8QXP_MEK
>  	bool "Support i.MX8QXP MEK board"
>  	select BOARD_LATE_INIT
>  	select IMX8QXP
> +	select FSL_CAAM
> +	select FSL_BLOB
> +	select ARCH_MISC_INIT
> +	select SPL_CRYPTO if SPL
>  
>  endchoice
>  
> diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-
> imx/imx8/cpu.c
> index 02db322f51..86ced79bb7 100644
> --- a/arch/arm/mach-imx/imx8/cpu.c
> +++ b/arch/arm/mach-imx/imx8/cpu.c
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
>   */
>  
>  #include <common.h>
> @@ -89,6 +89,20 @@ int arch_cpu_init_dm(void)
>  	return 0;
>  }
>  
> +#if defined(CONFIG_ARCH_MISC_INIT)
> +int arch_misc_init(void)
> +{
> +	struct udevice *dev;
> +	int ret;
> +
> +	ret = uclass_get_device_by_driver(UCLASS_MISC,
> DM_DRIVER_GET(caam_jr), &dev);
> +	if (ret)
> +		printf("Failed to initialize %s: %d\n", dev->name,
> ret);
> +
> +	return 0;
> +}
> +#endif
> +
>  int print_bootinfo(void)
>  {
>  	enum boot_device bt_dev = get_boot_device();
> diff --git a/board/freescale/imx8qm_mek/spl.c
> b/board/freescale/imx8qm_mek/spl.c
> index 944ba745c0..332a662dee 100644
> --- a/board/freescale/imx8qm_mek/spl.c
> +++ b/board/freescale/imx8qm_mek/spl.c
> @@ -1,7 +1,7 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
>  /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
>   *
> - * SPDX-License-Identifier:	GPL-2.0+
>   */
>  
>  #include <common.h>
> @@ -24,6 +24,8 @@ void spl_board_init(void)
>  {
>  	struct udevice *dev;
>  
> +	uclass_get_device_by_driver(UCLASS_MISC,
> DM_DRIVER_GET(imx8_scu), &dev);
> +
>  	uclass_find_first_device(UCLASS_MISC, &dev);
>  
>  	for (; dev; uclass_find_next_device(&dev)) {
> diff --git a/board/freescale/imx8qxp_mek/spl.c
> b/board/freescale/imx8qxp_mek/spl.c
> index ae6b64ff6e..2fa6840056 100644
> --- a/board/freescale/imx8qxp_mek/spl.c
> +++ b/board/freescale/imx8qxp_mek/spl.c
> @@ -1,7 +1,7 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
>  /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
>   *
> - * SPDX-License-Identifier:	GPL-2.0+
>   */
>  
>  #include <common.h>
> @@ -39,6 +39,8 @@ void spl_board_init(void)
>  {
>  	struct udevice *dev;
>  
> +	uclass_get_device_by_driver(UCLASS_MISC,
> DM_DRIVER_GET(imx8_scu), &dev);
> +
>  	uclass_find_first_device(UCLASS_MISC, &dev);
>  
>  	for (; dev; uclass_find_next_device(&dev)) {
> diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
> index 6d6c3f8d39..f550ab0e0a 100644
> --- a/drivers/crypto/fsl/Kconfig
> +++ b/drivers/crypto/fsl/Kconfig
> @@ -9,7 +9,7 @@ config FSL_CAAM
>  
>  config CAAM_64BIT
>  	bool
> -	default y if PHYS_64BIT && !ARCH_IMX8M
> +	default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8
>  	help
>  	  Select Crypto driver for 64 bits CAAM version
>  
> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> index 1b027f253c..ef133b670a 100644
> --- a/drivers/crypto/fsl/jr.c
> +++ b/drivers/crypto/fsl/jr.c
> @@ -25,6 +25,7 @@
>  #include <linux/delay.h>
>  #include <dm/root.h>
>  #include <dm/device-internal.h>
> +#include <power-domain.h>
>  
>  #define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size
> - 1))
>  #define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head)
> + 1, (size))
> @@ -786,6 +787,25 @@ int sec_init(void)
>  	return sec_init_idx(0);
>  }
>  
> +#ifdef CONFIG_ARCH_IMX8
> +static int jr_power_on(int subnode)
> +{
> +#if CONFIG_IS_ENABLED(POWER_DOMAIN)
> +	struct udevice __maybe_unused jr_dev;
> +	struct power_domain pd;
> +
> +	dev_set_ofnode(&jr_dev, offset_to_ofnode(subnode));
> +
> +	/* Need to power on Job Ring before access it */
> +	if (!power_domain_get(&jr_dev, &pd)) {
> +		if (power_domain_on(&pd))
> +			return -EINVAL;
> +	}
> +#endif
> +	return 0;
> +}
> +#endif
> +
>  #if CONFIG_IS_ENABLED(DM)
>  static int caam_jr_probe(struct udevice *dev)
>  {
> @@ -818,6 +838,10 @@ static int caam_jr_probe(struct udevice *dev)
>  				jr_node = jr_node >> 4;
>  			}
>  			caam->jrid = jr_node - 1;
> +#ifdef CONFIG_ARCH_IMX8
> +			if (jr_power_on(subnode))
> +				return -EINVAL;
> +#endif
>  			break;
>  		}
>  	}
> diff --git a/include/fsl_sec.h b/include/fsl_sec.h
> index c4121696f8..7b6e3e2c20 100644
> --- a/include/fsl_sec.h
> +++ b/include/fsl_sec.h
> @@ -3,7 +3,7 @@
>   * Common internal memory map for some Freescale SoCs
>   *
>   * Copyright 2014 Freescale Semiconductor, Inc.
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
>   */
>  
>  #ifndef __FSL_SEC_H
> @@ -194,12 +194,10 @@ typedef struct ccsr_sec {
>  #define SEC_CHAVID_LS_RNG_SHIFT		16
>  #define SEC_CHAVID_RNG_LS_MASK		0x000f0000
>  
> -#define CONFIG_JRSTARTR_JR0		0x00000001
> -
>  struct jr_regs {
>  #if defined(CONFIG_SYS_FSL_SEC_LE) && \
>  	!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
> -	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
> +	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) ||
> defined(CONFIG_IMX8))
>  	u32 irba_l;
>  	u32 irba_h;
>  #else
> @@ -214,7 +212,7 @@ struct jr_regs {
>  	u32 irja;
>  #if defined(CONFIG_SYS_FSL_SEC_LE) && \
>  	!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
> -	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
> +	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) ||
> defined(CONFIG_IMX8))
>  	u32 orba_l;
>  	u32 orba_h;
>  #else
> @@ -248,7 +246,7 @@ struct jr_regs {
>  struct sg_entry {
>  #if defined(CONFIG_SYS_FSL_SEC_LE) && \
>  	!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
> -	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
> +	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) ||
> defined(CONFIG_IMX8))
>  	uint32_t addr_lo;	/* Memory Address - lo */
>  	uint32_t addr_hi;	/* Memory Address of start of
> buffer - hi */
>  #else
> @@ -268,7 +266,7 @@ struct sg_entry {
>  };
>  
>  #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
> -	defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
> +	defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) ||
> defined(CONFIG_IMX8)
>  /* Job Ring Base Address */
>  #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
>  /* Secure Memory Offset varies accross versions */