[PATCH 08/23] ddr: imx8ulp: Change DRAM timing save area to 0x20055000

public inbox for u-boot@lists.denx.de
 help / color / mirror / Atom feed

From: Ye Li <ye.li@nxp.com>
To: sbabic@denx.de, u-boot@lists.denx.de
Cc: peng.fan@nxp.com, uboot-imx@nxp.com
Subject: [PATCH 08/23] ddr: imx8ulp: Change DRAM timing save area to 0x20055000
Date: Tue, 31 Jan 2023 16:42:19 +0800	[thread overview]
Message-ID: <1675154554-88217-9-git-send-email-ye.li@nxp.com> (raw)
In-Reply-To: <1675154554-88217-1-git-send-email-ye.li@nxp.com>

To align with ARM trusted firmware's change, adjust DRAM timing
save area to new position 0x20055000. So we can release the space
since 0x2006c000 for the NOBITS region of ARM trusted firmware

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
---
 drivers/ddr/imx/imx8ulp/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig
index 4284886..5448c33 100644
--- a/drivers/ddr/imx/imx8ulp/Kconfig
+++ b/drivers/ddr/imx/imx8ulp/Kconfig
@@ -13,6 +13,6 @@ config SAVED_DRAM_TIMING_BASE
 	help
 	  The DRAM config timing data need to be saved into sram
 	  for low power use.
-	default 0x2006c000
+	default 0x20055000
 
 endmenu
-- 
2.7.4

next prev parent reply	other threads:[~2023-01-31  8:48 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-31  8:42 [PATCH 00/23] Add i.MX8ULP A1 revision support Ye Li
2023-01-31  8:42 ` [PATCH 01/23] imx: imx8ulp: Fix MU device probe failure Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 02/23] imx: imx8ulp: Get chip revision from Sentinel Ye Li
2023-03-29 20:17   ` sbabic
2023-01-31  8:42 ` [PATCH 03/23] imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 part Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 04/23] imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 05/23] imx: imx8ulp: Remove the TRDC configure from A35 Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 06/23] imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 07/23] imx: imx8ulp: configure XRDC for DRAM access from S400 Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` Ye Li [this message]
2023-03-29 20:16   ` [PATCH 08/23] ddr: imx8ulp: Change DRAM timing save area to 0x20055000 sbabic
2023-01-31  8:42 ` [PATCH 09/23] imx: imx8ulp: Reconfigure MRC3 for SRAM0 access Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 10/23] imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 11/23] imx: imx8ulp: upower: replace magic number with macro Ye Li
2023-03-29 20:17   ` sbabic
2023-01-31  8:42 ` [PATCH 12/23] imx: imx8ulp: upower: make code cleaner Ye Li
2023-03-29 20:17   ` sbabic
2023-01-31  8:42 ` [PATCH 13/23] imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 14/23] imx: imx8ulp: Update clocks to meet max rate restrictions Ye Li
2023-03-29 20:15   ` sbabic
2023-01-31  8:42 ` [PATCH 15/23] imx: sentinel: Update S400 API get info message structure Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 16/23] misc: fuse: Update fuse mapping for 8ULP S400 API Ye Li
2023-03-29 20:15   ` sbabic
2023-01-31  8:42 ` [PATCH 17/23] misc: fuse: Lock 8ULP ECC-protected fuse when programming Ye Li
2023-03-29 20:15   ` sbabic
2023-01-31  8:42 ` [PATCH 18/23] ddr: imx: Update the ddr init flow on imx8ulp Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 19/23] imx8ulp_evk: Update the DDR timing Ye Li
2023-03-29 20:17   ` sbabic
2023-01-31  8:42 ` [PATCH 20/23] imx8ulp_evk: Change to use DDR driver Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 21/23] imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 22/23] imx8ulp_evk: disable overflow of port0 for LPAV Ye Li
2023-03-29 20:16   ` sbabic
2023-01-31  8:42 ` [PATCH 23/23] imx8ulp_evk: Clear data at fdt_addr_r before booting kernel Ye Li
2023-03-29 20:16   ` sbabic

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:4284886 dfblob:5448c33 )
 OR (
bs:"[PATCH 08/23] ddr: imx8ulp: Change DRAM timing save area to 0x20055000" )
	(help)

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1675154554-88217-9-git-send-email-ye.li@nxp.com \
    --to=ye.li@nxp.com \
    --cc=peng.fan@nxp.com \
    --cc=sbabic@denx.de \
    --cc=u-boot@lists.denx.de \
    --cc=uboot-imx@nxp.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Be sure your reply has a Subject: header at the top and a blank line before the message body.

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox