[PATCH 04/23] imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD

Ye Li
2023-01-31T08:45:59Z

iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
them in SPL to allow access to DDR from A35 and APD PER masters

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8ulp/rdc.c | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 6d2adcf..d664437 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -276,6 +276,16 @@ void xrdc_init_mda(void)

void xrdc_init_mrc(void)
{
+ /* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
+ xrdc_config_mrc_w0_w1(4, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+ xrdc_config_mrc_dx_perm(4, 0, 1, 1);
+ xrdc_config_mrc_dx_perm(4, 0, 7, 1);
+ xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF);
+
+ xrdc_config_mrc_w0_w1(5, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+ xrdc_config_mrc_dx_perm(5, 0, 1, 1);
+ xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
+
/* The MRC8 is for SRAM1 */
xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000);
/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */
--
2.7.4