[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

["Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>]

Hi Alison,

On Tuesday, May 21, 2013 11:03:01 AM, Alison Wang wrote:
> MVF600TWR is a board based on Vybrid MVF600 SoC.
> 
> This patch adds basic support for Vybrid MVF600TWR board.
> 
> Signed-off-by: Alison Wang <b18965@freescale.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>

[...]

> diff --git a/board/freescale/mvf600twr/mvf600twr.c
> b/board/freescale/mvf600twr/mvf600twr.c
> new file mode 100644
> index 0000000..71ee12b
> --- /dev/null
> +++ b/board/freescale/mvf600twr/mvf600twr.c
> @@ -0,0 +1,413 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/mvf_pins.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/clock.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> +			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
> +
> +#define ESDHC_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | \
> +			PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | \
> +			PAD_CTL_OBE_IBE_ENABLE)

With the changes that I have suggested in my review of your IOMUX patch,
ESDHC_PAD_CTRL could be simplified by removing PAD_CTL_PUE.

And without those changes, UART_PAD_CTRL and ENET_PAD_CTRL in your current code
set pull values that are actually unused (unless the corresponding PKE/PUE bits
do not exist and default to pull in the pad control registers used with these
definitions).

> +
> +#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
> +			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
> +
> +#define DDR_PAD_CTRL	PAD_CTL_DSE_25ohm

MUX_PAD_CTRL() could be added to the 4 pad control definitions above in order to
avoid repeating it everywhere below. But using MUX_PAD_CTRL() relies on the fact
that the pad control values in mvf_pins.h are all 0 (which is the case, but this
is dangerous if this is changed later), so a better approach could be to use
NEW_PAD_CTRL(), e.g.:
        NEW_PAD_CTRL(MVF600_PAD_DDR_A15__DDR_A_15, DDR_PAD_CTRL),
instead of:
        MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),

> +
> +iomux_v3_cfg_t const ddr_pads[] = {
> +	MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A14__DDR_A_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A13__DDR_A_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A12__DDR_A_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A11__DDR_A_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A10__DDR_A_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A9__DDR_A_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A8__DDR_A_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A7__DDR_A_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A6__DDR_A_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A5__DDR_A_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A4__DDR_A_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A3__DDR_A_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A2__DDR_A_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A1__DDR_A_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_BA2__DDR_BA_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_BA1__DDR_BA_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_BA0__DDR_BA_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_CAS__DDR_CAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_CKE__DDR_CKE_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_CLK__DDR_CLK_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_CS__DDR_CS_B_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D15__DDR_D_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D14__DDR_D_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D13__DDR_D_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D12__DDR_D_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D11__DDR_D_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D10__DDR_D_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D9__DDR_D_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D8__DDR_D_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D7__DDR_D_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D6__DDR_D_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D5__DDR_D_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D4__DDR_D_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D3__DDR_D_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D2__DDR_D_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D1__DDR_D_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D0__DDR_D_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_DQM1__DDR_DQM_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_DQM0__DDR_DQM_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_DQS1__DDR_DQS_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_DQS0__DDR_DQS_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_RAS__DDR_RAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_WE__DDR_WE_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_ODT1__DDR_ODT_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_ODT0__DDR_ODT_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const uart1_pads[] = {
> +	MVF600_PAD_PTB4__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MVF600_PAD_PTB5__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const enet0_pads[] = {
> +	MVF600_PAD_PTA6__RMII0_CLKIN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC1__RMII0_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC0__RMII0_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC2__RMII0_CRS_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC3__RMII0_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC4__RMII0_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC5__RMII0_RXER | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC6__RMII0_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC7__RMII0_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC8__RMII0_TXEN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const esdhc1_pads[] = {
> +	MVF600_PAD_PTA24__ESDHC1_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	MVF600_PAD_PTA25__ESDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	MVF600_PAD_PTA26__ESDHC1_DAT0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	MVF600_PAD_PTA27__ESDHC1_DAT1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	MVF600_PAD_PTA28__ESDHC1_DAT2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	MVF600_PAD_PTA29__ESDHC1_DAT3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +};

[...]

Best regards,
Beno?t