From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1435DC4338F for ; Thu, 12 Aug 2021 20:20:57 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1ACF860EB5 for ; Thu, 12 Aug 2021 20:20:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1ACF860EB5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 91E3F82DAA; Thu, 12 Aug 2021 22:20:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rVakDiA1"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3BFAB82DB3; Thu, 12 Aug 2021 22:20:52 +0200 (CEST) Received: from mail-qk1-x72d.google.com (mail-qk1-x72d.google.com [IPv6:2607:f8b0:4864:20::72d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E8CDC82DA2 for ; Thu, 12 Aug 2021 22:20:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qk1-x72d.google.com with SMTP id n11so3351790qkk.1 for ; Thu, 12 Aug 2021 13:20:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:subject:to:cc:references:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=VNaLelqIJOze6qJOhFv5u0uIP6+UthwizMfewjIbeRc=; b=rVakDiA1nvBYV3/rp7245T/jqP/FCPGir8AAcGaqqtNHaK+6xlVMfwCEwA0j4qICRF uTCQIXaLq8KywJ+BN4OaCkJy5byiaL/+ihZB6EonyBGO8hf1xRNiFMtvYPoHpkYfO6Ue 2vakeQjEAxWExL2Kopm5k3+BdNOVNYSzwBgu1n2vReJP6R0RgGOex2mMtpkmQ+VwViiT Pwf5ts+rlz0FpeCSh06Xkt9RxZuJxKRzvcQ5M2IxwO8U70X6t37DPV0jtUAFHigb7O5J 80y2098GURYxCzhQVqlHZThPpowf8fdOe3Fjq641YXkxKtVMz6GDpniqMUOH9Dnb5rkt DwJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:references:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=VNaLelqIJOze6qJOhFv5u0uIP6+UthwizMfewjIbeRc=; b=bpanqwRKL+fGKbq9baSPii3wZ4qyvG/xRcrv12ANiLZhDilMHD9MW3Bz6m1e61xBnR ibn6bf1XL9n0HzfBcByXVU3GbmWPTRDJzNSSAgQ/WEdWaxWl6myUWQSTAsEanj77AFaN ZpTZN14o5Cs2t9Ac1G8GeKyhR7JUVWcO2gpRQ2UyKsrem9X8W8JA+Ykivmc6Bj0HPJyE B37yyUgM9pMPSLdAFYKvLQpgWvuq1gBlq3JJqnasXRD/Fv/zDYuh0EDPSsC7m+HW206O dpqHRF4s38sDmorFD8cG0rJFjqbsn9g6kCm4IPx8K6FGs+1wOjQ46aE0itE2vTGmH6tG 74Ow== X-Gm-Message-State: AOAM531C2oa+Ckfq4cYFtoLhk4KnCXX4x/53Le8S7JkfMV+Aj0Z1zkqp KAlh4deFDxcBGhqGuzzupgzLwmCqmXM= X-Google-Smtp-Source: ABdhPJw5O2Z+jeY7yXiu0Iukm94lt5Dilemz92UTaVeJGbH/vqzmxc0LyjLTJwHsuNo4kMPltS49Xw== X-Received: by 2002:ae9:f70f:: with SMTP id s15mr6328768qkg.437.1628799646326; Thu, 12 Aug 2021 13:20:46 -0700 (PDT) Received: from [192.168.1.201] (pool-108-45-127-224.washdc.fios.verizon.net. [108.45.127.224]) by smtp.googlemail.com with ESMTPSA id b3sm1639221qto.0.2021.08.12.13.20.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Aug 2021 13:20:45 -0700 (PDT) From: Sean Anderson Subject: Re: [PATCH v2 3/6] riscv: lib: introduce cache_init interface To: Zong Li Cc: rick@andestech.com, Leo Liang , Bin Meng , Green Wan , Paul Walmsley , sjg@chromium.org, u-boot@lists.denx.de References: <20210803044444.14032-1-zong.li@sifive.com> <20210803044444.14032-4-zong.li@sifive.com> Message-ID: <1734da12-38df-e79e-2fdb-137726890043@gmail.com> Date: Thu, 12 Aug 2021 16:20:45 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 8/10/21 2:57 AM, Zong Li wrote: > On Tue, Aug 10, 2021 at 12:47 PM Sean Anderson wrote: >> >> On 8/3/21 12:44 AM, Zong Li wrote: >>> Add an interface for cache initialization. Each platform can overwrite >>> this weak function by their own implementation, such as sifive_cache in >>> this patch. >> >> Can we call this enable_caches instead of cache_init? This function is >> called by initr_caches in board_r.c for ARM. There's even an >> eight-year-old TODO on the subject. >> > > I had considered use it, The reason I finally used cache_init here is > that it seems to me that cache_init would be more flexible for risc-v > platforms to do not only cache enable, but also various > platform-specific initialization of cache, even they could decide the > time to invoke cache_init if there is particular initialization > sequence. Do you have some example in mind? > If you think that cache_init is OK to you, I would prefer to > retain cache_init. I can still use enable_caches instead of cache_init > if you think that it is a better way. Please let me know your thoughts > and thanks for your review. I would like to reduce the proliferation of different cache enable functions. Right now we have (i|d)cache_enable which are RISC-V-specific and called very early during boot; cache_enable, which must be called manually; enable_caches, which is implemented only for ARM; and your proposed cache_init. I don't think there is need for yet another way to accomplish the same thing. --Sean >>> >>> Signed-off-by: Zong Li >>> --- >>> arch/riscv/Kconfig | 5 +++++ >>> arch/riscv/include/asm/cache.h | 1 + >>> arch/riscv/lib/Makefile | 1 + >>> arch/riscv/lib/cache.c | 5 +++++ >>> arch/riscv/lib/sifive_cache.c | 27 +++++++++++++++++++++++++++ >>> 5 files changed, 39 insertions(+) >>> create mode 100644 arch/riscv/lib/sifive_cache.c >>> >>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >>> index 4b0c3dffa6..ec651fe0a4 100644 >>> --- a/arch/riscv/Kconfig >>> +++ b/arch/riscv/Kconfig >>> @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT >>> The SiFive CLINT block holds memory-mapped control and status registers >>> associated with software and timer interrupts. >>> >>> +config SIFIVE_CACHE >>> + bool >>> + help >>> + This enables the operations to configure SiFive cache >>> + >>> config ANDES_PLIC >>> bool >>> depends on RISCV_MMODE || SPL_RISCV_MMODE >>> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h >>> index ec8fe201d3..6ebb2b4329 100644 >>> --- a/arch/riscv/include/asm/cache.h >>> +++ b/arch/riscv/include/asm/cache.h >>> @@ -9,6 +9,7 @@ >>> >>> /* cache */ >>> void cache_flush(void); >>> +int cache_init(void); >>> >>> /* >>> * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. >>> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile >>> index c4cc41434b..06020fcc2a 100644 >>> --- a/arch/riscv/lib/Makefile >>> +++ b/arch/riscv/lib/Makefile >>> @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o >>> obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o >>> obj-$(CONFIG_CMD_GO) += boot.o >>> obj-y += cache.o >>> +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o >>> ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) >>> obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o >>> obj-$(CONFIG_ANDES_PLIC) += andes_plic.o >>> diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c >>> index b1d42bcc2b..2cd66504c6 100644 >>> --- a/arch/riscv/lib/cache.c >>> +++ b/arch/riscv/lib/cache.c >>> @@ -70,3 +70,8 @@ __weak int dcache_status(void) >>> { >>> return 0; >>> } >>> + >>> +__weak int cache_init(void) >>> +{ >>> + return 0; >>> +} >>> diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c >>> new file mode 100644 >>> index 0000000000..94e84e024e >>> --- /dev/null >>> +++ b/arch/riscv/lib/sifive_cache.c >>> @@ -0,0 +1,27 @@ >>> +// SPDX-License-Identifier: GPL-2.0+ >>> +/* >>> + * Copyright (C) 2021 SiFive, Inc >>> + */ >>> + >>> +#include >>> +#include >>> +#include >>> + >>> +int cache_init(void) >>> +{ >>> + struct udevice *dev; >>> + int ret; >>> + >>> + /* Enable ways of ccache */ >>> + ret = uclass_get_device_by_driver(UCLASS_CACHE, >>> + DM_DRIVER_GET(sifive_ccache), >>> + &dev); >>> + if (ret) >>> + return log_msg_ret("Cannot enable cache ways", ret); >>> + >>> + ret = cache_enable(dev); >>> + if (ret) >>> + return log_msg_ret("ccache enable failed", ret); >>> + >>> + return 0; >>> +} >>> >> >> Otherwise LGTM