* [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support
@ 2016-07-18 1:06 Andreas Färber
2016-07-18 1:06 ` [U-Boot] [PATCH 1/2] dts: Import rk3368-geekbox.dts Andreas Färber
` (3 more replies)
0 siblings, 4 replies; 17+ messages in thread
From: Andreas Färber @ 2016-07-18 1:06 UTC (permalink / raw)
To: u-boot
Hi,
This series adds initial support for RK3368 SoC and GeekBox.
For more details see the commit message.
Will need to be rebased onto Heiko's cleanups and Kever's RK3399 series.
Regards,
Andreas
Cc: Simon Glass <sjg@chromium.org>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Heiko St?bner <heiko@sntech.de>
Andreas F?rber (2):
dts: Import rk3368-geekbox.dts
ARM64: rockchip: Add initial support for RK3368 based GeekBox
arch/arm/Kconfig | 4 -
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/rk3368-geekbox.dts | 319 ++++++++++
arch/arm/dts/rk3368.dtsi | 1082 ++++++++++++++++++++++++++++++++
arch/arm/mach-rockchip/Kconfig | 14 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3368/Kconfig | 14 +
arch/arm/mach-rockchip/rk3368/Makefile | 7 +
arch/arm/mach-rockchip/rk3368/rk3368.c | 28 +
board/geekbuying/geekbox/Kconfig | 15 +
board/geekbuying/geekbox/Makefile | 7 +
board/geekbuying/geekbox/geekbox.c | 26 +
configs/geekbox_defconfig | 20 +
include/configs/geekbox.h | 19 +
include/configs/rk3368_common.h | 47 ++
include/dt-bindings/clock/rk3368-cru.h | 384 ++++++++++++
16 files changed, 1985 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/dts/rk3368-geekbox.dts
create mode 100644 arch/arm/dts/rk3368.dtsi
create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c
create mode 100644 board/geekbuying/geekbox/Kconfig
create mode 100644 board/geekbuying/geekbox/Makefile
create mode 100644 board/geekbuying/geekbox/geekbox.c
create mode 100644 configs/geekbox_defconfig
create mode 100644 include/configs/geekbox.h
create mode 100644 include/configs/rk3368_common.h
create mode 100644 include/dt-bindings/clock/rk3368-cru.h
--
2.6.6
^ permalink raw reply [flat|nested] 17+ messages in thread* [U-Boot] [PATCH 1/2] dts: Import rk3368-geekbox.dts 2016-07-18 1:06 [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support Andreas Färber @ 2016-07-18 1:06 ` Andreas Färber 2016-07-18 11:56 ` Simon Glass 2016-07-18 1:06 ` [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox Andreas Färber ` (2 subsequent siblings) 3 siblings, 1 reply; 17+ messages in thread From: Andreas Färber @ 2016-07-18 1:06 UTC (permalink / raw) To: u-boot Unmodified from Linux kernel v4.7-rc6. Signed-off-by: Andreas F?rber <afaerber@suse.de> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3368-geekbox.dts | 319 ++++++++++ arch/arm/dts/rk3368.dtsi | 1081 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/rk3368-cru.h | 384 ++++++++++++ 4 files changed, 1786 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3368-geekbox.dts create mode 100644 arch/arm/dts/rk3368.dtsi create mode 100644 include/dt-bindings/clock/rk3368-cru.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 73e334e..fd355e3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -32,7 +32,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-jerry.dtb \ rk3288-rock2-square.dtb \ rk3288-evb.dtb \ - rk3036-sdk.dtb + rk3036-sdk.dtb \ + rk3368-geekbox.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ diff --git a/arch/arm/dts/rk3368-geekbox.dts b/arch/arm/dts/rk3368-geekbox.dts new file mode 100644 index 0000000..46cdddf --- /dev/null +++ b/arch/arm/dts/rk3368-geekbox.dts @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2016 Andreas F?rber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "GeekBox"; + compatible = "geekbuying,geekbox", "rockchip,rk3368"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory at 0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + blue { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + label = "geekbox:blue:led"; + default-state = "on"; + }; + + red { + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + label = "geekbox:red:led"; + default-state = "off"; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + clock-frequency = <150000000>; + disable-wp; + keep-power-in-suspend; + non-removable; + num-slots = <1>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_flash>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +}; + +&gmac { + status = "okay"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic at 1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&pmic_sleep>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + }; + + vcc18_flash: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_flash"; + }; + + vcc33_lcd: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_lcd"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + }; + + vcca_18: LDO_REG4 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_18"; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + }; + + vcc_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + }; + + vcc_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lan"; + }; + }; + }; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_sleep: pmic-sleep { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <0>; /* CRU */ + rockchip,hw-tshut-polarity = <1>; /* high */ +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi new file mode 100644 index 0000000..8b4a7c9 --- /dev/null +++ b/arch/arm/dts/rk3368.dtsi @@ -0,0 +1,1081 @@ +/* + * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/rk3368-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "rockchip,rk3368"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &gmac; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + core2 { + cpu = <&cpu_b2>; + }; + core3 { + cpu = <&cpu_b3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <0x3fffffff>; + exit-latency-us = <0x40000000>; + min-residency-us = <0xffffffff>; + }; + }; + + cpu_l0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_l1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_l2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_l3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_b0: cpu at 100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x100>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_b1: cpu at 101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x101>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_b2: cpu at 102 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x102>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_b3: cpu at 103 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x103>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, + <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, + <&cpu_b2>, <&cpu_b3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + sdmmc: dwmmc at ff0c0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0c0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdio0: dwmmc at ff0d0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0d0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, + <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + emmc: dwmmc at ff0f0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0f0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + saradc: saradc at ff100000 { + compatible = "rockchip,saradc"; + reg = <0x0 0xff100000 0x0 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + + spi0: spi at ff110000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff110000 0x0 0x1000>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi at ff120000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff120000 0x0 0x1000>; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi at ff130000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff130000 0x0 0x1000>; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c at ff140000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff140000 0x0 0x1000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c3: i2c at ff150000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + i2c4: i2c at ff160000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + status = "disabled"; + }; + + i2c5: i2c at ff170000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff170000 0x0 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C5>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_xfer>; + status = "disabled"; + }; + + uart0: serial at ff180000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial at ff190000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff190000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial at ff1b0000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1b0000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial at ff1c0000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1c0000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + thermal-zones { + cpu { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <115000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc at ff280000 { + compatible = "rockchip,rk3368-tsadc"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + + gmac: ethernet at ff290000 { + compatible = "rockchip,rk3368-gmac"; + reg = <0x0 0xff290000 0x0 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_MAC>, + <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, + <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; + clock-names = "stmmaceth", + "mac_clk_rx", "mac_clk_tx", + "clk_mac_ref", "clk_mac_refout", + "aclk_mac", "pclk_mac"; + status = "disabled"; + }; + + usb_host0_ehci: usb at ff500000 { + compatible = "generic-ehci"; + reg = <0x0 0xff500000 0x0 0x100>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST0>; + clock-names = "usbhost"; + status = "disabled"; + }; + + usb_otg: usb at ff580000 { + compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff580000 0x0 0x40000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; + status = "disabled"; + }; + + i2c0: i2c at ff650000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff650000 0x0 0x1000>; + clocks = <&cru PCLK_I2C0>; + clock-names = "i2c"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c at ff660000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff660000 0x0 0x1000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + pwm0: pwm at ff680000 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm at ff680010 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm at ff680020 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680020 0x0 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm at ff680030 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + uart2: serial at ff690000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff690000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + mbox: mbox at ff6b0000 { + compatible = "rockchip,rk3368-mailbox"; + reg = <0x0 0xff6b0000 0x0 0x1000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + }; + + pmugrf: syscon at ff738000 { + compatible = "rockchip,rk3368-pmugrf", "syscon"; + reg = <0x0 0xff738000 0x0 0x1000>; + }; + + cru: clock-controller at ff760000 { + compatible = "rockchip,rk3368-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + grf: syscon at ff770000 { + compatible = "rockchip,rk3368-grf", "syscon"; + reg = <0x0 0xff770000 0x0 0x1000>; + }; + + wdt: watchdog at ff800000 { + compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; + reg = <0x0 0xff800000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer at ff810000 { + compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xff810000 0x0 0x20>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + }; + + gic: interrupt-controller at ffb71000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x0 0xffb71000 0x0 0x1000>, + <0x0 0xffb72000 0x0 0x1000>, + <0x0 0xffb74000 0x0 0x2000>, + <0x0 0xffb76000 0x0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3368-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + gpio0: gpio0 at ff750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff750000 0x0 0x100>; + clocks = <&cru PCLK_GPIO0>; + interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio1: gpio1 at ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff780000 0x0 0x100>; + clocks = <&cru PCLK_GPIO1>; + interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio2: gpio2 at ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff790000 0x0 0x100>; + clocks = <&cru PCLK_GPIO2>; + interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio3: gpio3 at ff7a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff7a0000 0x0 0x100>; + clocks = <&cru PCLK_GPIO3>; + interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_pwr: emmc-pwr { + rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, + <1 19 RK_FUNC_2 &pcfg_pull_up>, + <1 20 RK_FUNC_2 &pcfg_pull_up>, + <1 21 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, + <1 19 RK_FUNC_2 &pcfg_pull_up>, + <1 20 RK_FUNC_2 &pcfg_pull_up>, + <1 21 RK_FUNC_2 &pcfg_pull_up>, + <1 22 RK_FUNC_2 &pcfg_pull_up>, + <1 23 RK_FUNC_2 &pcfg_pull_up>, + <1 24 RK_FUNC_2 &pcfg_pull_up>, + <1 25 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, + <3 24 RK_FUNC_1 &pcfg_pull_none>, + <3 19 RK_FUNC_1 &pcfg_pull_none>, + <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 15 RK_FUNC_1 &pcfg_pull_none>, + <3 16 RK_FUNC_1 &pcfg_pull_none>, + <3 17 RK_FUNC_1 &pcfg_pull_none>, + <3 18 RK_FUNC_1 &pcfg_pull_none>, + <3 25 RK_FUNC_1 &pcfg_pull_none>, + <3 20 RK_FUNC_1 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, + <3 24 RK_FUNC_1 &pcfg_pull_none>, + <3 19 RK_FUNC_1 &pcfg_pull_none>, + <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 15 RK_FUNC_1 &pcfg_pull_none>, + <3 16 RK_FUNC_1 &pcfg_pull_none>, + <3 20 RK_FUNC_1 &pcfg_pull_none>, + <3 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, + <0 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, + <2 22 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, + <3 31 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, + <1 17 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, + <3 25 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { + rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, + <3 27 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, + <2 29 RK_FUNC_1 &pcfg_pull_up>, + <2 30 RK_FUNC_1 &pcfg_pull_up>, + <2 31 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdio0_cd: sdio0-cd { + rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_wp: sdio0-wp { + rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_pwr: sdio0-pwr { + rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_bkpwr: sdio0-bkpwr { + rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_int: sdio0-int { + rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, + <2 6 RK_FUNC_1 &pcfg_pull_up>, + <2 7 RK_FUNC_1 &pcfg_pull_up>, + <2 8 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_clk: spi2-clk { + rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { + rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { + rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { + rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, + <2 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, + <0 21 RK_FUNC_3 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, + <2 5 RK_FUNC_2 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, + <3 30 RK_FUNC_3 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, + <0 26 RK_FUNC_3 &pcfg_pull_none>; + }; + + uart4_cts: uart4-cts { + rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; + }; + + uart4_rts: uart4-rts { + rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h new file mode 100644 index 0000000..9c5dd9b --- /dev/null +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H + +/* core clocks */ +#define PLL_APLLB 1 +#define PLL_APLLL 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define ARMCLKB 7 +#define ARMCLKL 8 + +/* sclk gates (special clocks) */ +#define SCLK_GPU_CORE 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO0 69 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_SARADC 73 +#define SCLK_NANDC0 75 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_UART3 80 +#define SCLK_UART4 81 +#define SCLK_I2S_8CH 82 +#define SCLK_SPDIF_8CH 83 +#define SCLK_I2S_2CH 84 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_TIMER6 91 +#define SCLK_OTGPHY0 93 +#define SCLK_OTG_ADP 96 +#define SCLK_HSICPHY480M 97 +#define SCLK_HSICPHY12M 98 +#define SCLK_MACREF 99 +#define SCLK_VOP0_PWM 100 +#define SCLK_MAC_RX 102 +#define SCLK_MAC_TX 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_HDCP 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 +#define SCLK_I2S_8CH_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M 122 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_PMU 125 +#define SCLK_SFC 126 +#define SCLK_MAC 127 +#define SCLK_MACREF_OUT 128 + +#define DCLK_VOP 190 +#define MCLK_CRYPTO 191 + +/* aclk gates */ +#define ACLK_GPU_MEM 192 +#define ACLK_GPU_CFG 193 +#define ACLK_DMAC_BUS 194 +#define ACLK_DMAC_PERI 195 +#define ACLK_PERI_MMU 196 +#define ACLK_GMAC 197 +#define ACLK_VOP 198 +#define ACLK_VOP_IEP 199 +#define ACLK_RGA 200 +#define ACLK_HDCP 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NOC 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NOC 206 +#define ACLK_VIDEO 208 +#define ACLK_BUS 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_PMUGRF 324 +#define PCLK_MAILBOX 325 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_UART3 344 +#define PCLK_UART4 345 +#define PCLK_TSADC 346 +#define PCLK_SARADC 347 +#define PCLK_SIM 348 +#define PCLK_GMAC 349 +#define PCLK_PWM0 350 +#define PCLK_PWM1 351 +#define PCLK_TIMER0 353 +#define PCLK_TIMER1 354 +#define PCLK_EDP_CTRL 355 +#define PCLK_MIPI_DSI0 356 +#define PCLK_MIPI_CSI 358 +#define PCLK_HDCP 359 +#define PCLK_HDMI_CTRL 360 +#define PCLK_VIO_H2P 361 +#define PCLK_BUS 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_DDRPHY 365 +#define PCLK_ISP 366 +#define PCLK_VIP 367 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_SFC 448 +#define HCLK_OTG0 449 +#define HCLK_HOST0 450 +#define HCLK_HOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S_2CH 462 +#define HCLK_I2S_8CH 463 +#define HCLK_SPDIF 464 +#define HCLK_VOP 465 +#define HCLK_ROM 467 +#define HCLK_IEP 468 +#define HCLK_ISP 469 +#define HCLK_RGA 470 +#define HCLK_VIO_AHB_ARBI 471 +#define HCLK_VIO_NOC 472 +#define HCLK_VIP 473 +#define HCLK_VIO_H2P 474 +#define HCLK_VIO_HDCPMMU 475 +#define HCLK_VIDEO 476 +#define HCLK_BUS 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE_B0 0 +#define SRST_CORE_B1 1 +#define SRST_CORE_B2 2 +#define SRST_CORE_B3 3 +#define SRST_CORE_B0_PO 4 +#define SRST_CORE_B1_PO 5 +#define SRST_CORE_B2_PO 6 +#define SRST_CORE_B3_PO 7 +#define SRST_L2_B 8 +#define SRST_ADB_B 9 +#define SRST_PD_CORE_B_NIU 10 +#define SRST_PDBUS_STRSYS 11 +#define SRST_SOCDBG_B 14 +#define SRST_CORE_B_DBG 15 + +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_I2S8CH 23 +#define SRST_MAILBOX 24 +#define SRST_I2S2CH 25 +#define SRST_EFUSE_256 26 +#define SRST_MCU_SYS 28 +#define SRST_MCU_PO 29 +#define SRST_MCU_NOC 30 +#define SRST_EFUSE 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_PMUGRF 41 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +#define SRST_DWPWM 48 +#define SRST_MMC_PERI 49 +#define SRST_PERIPH_MMU 50 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH_AXI 57 +#define SRST_PERIPH_AHB 58 +#define SRST_PERIPH_APB 59 +#define SRST_PERIPH_NIU 60 +#define SRST_PDPERI_AHB_ARBI 61 +#define SRST_EMEM 62 +#define SRST_USB_PERI 63 + +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_GPS 67 +#define SRST_RKPWM 69 +#define SRST_USBHOST0 72 +#define SRST_HSIC 73 +#define SRST_HSIC_AUX 74 +#define SRST_HSIC_PHY 75 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_SFC 79 + +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SPI2 85 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 + +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 +#define SRST_EDP_24M 111 + +#define SRST_VIDEO_AXI 112 +#define SRST_VIDEO_AHB 113 +#define SRST_MIPIDPHYTX 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDPHYRX 116 +#define SRST_MIPICSI 117 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_EDP 122 +#define SRST_PMU_PVTM 123 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 +#define SRST_GPU_SYS 126 +#define SRST_GPU_MEM_NIU 127 + +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHOST0_PHY 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBOTG_UTMI 138 +#define SRST_USBHOST1_UTMI 139 +#define SRST_USB_ADP 141 + +#define SRST_CORESIGHT 144 +#define SRST_PD_CORE_AHB_NOC 145 +#define SRST_PD_CORE_APB_NOC 146 +#define SRST_GIC 148 +#define SRST_LCDC_PWM0 149 +#define SRST_RGA_H2P_BRG 153 +#define SRST_VIDEO 154 +#define SRST_GPU_CFG_NIU 157 +#define SRST_TSADC 159 + +#define SRST_DDRPHY0 160 +#define SRST_DDRPHY0_APB 161 +#define SRST_DDRCTRL0 162 +#define SRST_DDRCTRL0_APB 163 +#define SRST_VIDEO_NIU 165 +#define SRST_VIDEO_NIU_AHB 167 +#define SRST_DDRMSCH0 170 +#define SRST_PDBUS_AHB 173 +#define SRST_CRYPTO 174 + +#define SRST_UART0 179 +#define SRST_UART1 180 +#define SRST_UART2 181 +#define SRST_UART3 182 +#define SRST_UART4 183 +#define SRST_SIMC 186 +#define SRST_TSP 188 +#define SRST_TSP_CLKIN0 189 + +#define SRST_CORE_L0 192 +#define SRST_CORE_L1 193 +#define SRST_CORE_L2 194 +#define SRST_CORE_L3 195 +#define SRST_CORE_L0_PO 195 +#define SRST_CORE_L1_PO 197 +#define SRST_CORE_L2_PO 198 +#define SRST_CORE_L3_PO 199 +#define SRST_L2_L 200 +#define SRST_ADB_L 201 +#define SRST_PD_CORE_L_NIU 202 +#define SRST_CCI_SYS 203 +#define SRST_CCI_DDR 204 +#define SRST_CCI 205 +#define SRST_SOCDBG_L 206 +#define SRST_CORE_L_DBG 207 + +#define SRST_CORE_B0_NC 208 +#define SRST_CORE_B0_PO_NC 209 +#define SRST_L2_B_NC 210 +#define SRST_ADB_B_NC 211 +#define SRST_PD_CORE_B_NIU_NC 212 +#define SRST_PDBUS_STRSYS_NC 213 +#define SRST_CORE_L0_NC 214 +#define SRST_CORE_L0_PO_NC 215 +#define SRST_L2_L_NC 216 +#define SRST_ADB_L_NC 217 +#define SRST_PD_CORE_L_NIU_NC 218 +#define SRST_CCI_SYS_NC 219 +#define SRST_CCI_DDR_NC 220 +#define SRST_CCI_NC 221 +#define SRST_TRACE_NC 222 + +#define SRST_TIMER00 224 +#define SRST_TIMER01 225 +#define SRST_TIMER02 226 +#define SRST_TIMER03 227 +#define SRST_TIMER04 228 +#define SRST_TIMER05 229 +#define SRST_TIMER10 230 +#define SRST_TIMER11 231 +#define SRST_TIMER12 232 +#define SRST_TIMER13 233 +#define SRST_TIMER14 234 +#define SRST_TIMER15 235 +#define SRST_TIMER0_APB 236 +#define SRST_TIMER1_APB 237 + +#endif -- 2.6.6 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 1/2] dts: Import rk3368-geekbox.dts 2016-07-18 1:06 ` [U-Boot] [PATCH 1/2] dts: Import rk3368-geekbox.dts Andreas Färber @ 2016-07-18 11:56 ` Simon Glass 0 siblings, 0 replies; 17+ messages in thread From: Simon Glass @ 2016-07-18 11:56 UTC (permalink / raw) To: u-boot On 17 July 2016 at 19:06, Andreas F?rber <afaerber@suse.de> wrote: > Unmodified from Linux kernel v4.7-rc6. > > Signed-off-by: Andreas F?rber <afaerber@suse.de> > --- > arch/arm/dts/Makefile | 3 +- > arch/arm/dts/rk3368-geekbox.dts | 319 ++++++++++ > arch/arm/dts/rk3368.dtsi | 1081 ++++++++++++++++++++++++++++++++ > include/dt-bindings/clock/rk3368-cru.h | 384 ++++++++++++ > 4 files changed, 1786 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/rk3368-geekbox.dts > create mode 100644 arch/arm/dts/rk3368.dtsi > create mode 100644 include/dt-bindings/clock/rk3368-cru.h Acked-by: Simon Glass <sjg@chromium.org> ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox 2016-07-18 1:06 [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support Andreas Färber 2016-07-18 1:06 ` [U-Boot] [PATCH 1/2] dts: Import rk3368-geekbox.dts Andreas Färber @ 2016-07-18 1:06 ` Andreas Färber 2016-07-18 1:22 ` Andreas Färber ` (2 more replies) 2016-08-06 4:30 ` [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support Simon Glass 2016-08-29 7:17 ` Peter Robinson 3 siblings, 3 replies; 17+ messages in thread From: Andreas Färber @ 2016-07-18 1:06 UTC (permalink / raw) To: u-boot The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. The GeekBox is a TV box from GeekBuying, based on an MXM3 module. The module can be used with base boards such as the GeekBox Landingship. This adds basic support to chain-load U-Boot from Rockchip's miniloader. $ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img # ./utils/upgrade_tool di uboot u-boot.img Implemented is the serial console, but no boot media drivers yet. Note that flashing the resulting U-Boot will not allow you to enter the rockusb mode any more via "Update" button. Instead, you will need to short two pins on the bottom of the module to enter MaskRom mode and re-flash the loader: # ./utils/upgrade_tool ul ./lollipop_u-boot/RK3368MiniLoaderAll_V2.40.bin # ./utils/upgrade_tool di uboot u-boot.img Signed-off-by: Andreas F?rber <afaerber@suse.de> --- arch/arm/Kconfig | 4 --- arch/arm/dts/rk3368.dtsi | 1 + arch/arm/mach-rockchip/Kconfig | 14 ++++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3368/Kconfig | 14 ++++++++++ arch/arm/mach-rockchip/rk3368/Makefile | 7 +++++ arch/arm/mach-rockchip/rk3368/rk3368.c | 28 ++++++++++++++++++++ board/geekbuying/geekbox/Kconfig | 15 +++++++++++ board/geekbuying/geekbox/Makefile | 7 +++++ board/geekbuying/geekbox/geekbox.c | 26 +++++++++++++++++++ configs/geekbox_defconfig | 20 +++++++++++++++ include/configs/geekbox.h | 19 ++++++++++++++ include/configs/rk3368_common.h | 47 ++++++++++++++++++++++++++++++++++ 13 files changed, 199 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c create mode 100644 board/geekbuying/geekbox/Kconfig create mode 100644 board/geekbuying/geekbox/Makefile create mode 100644 board/geekbuying/geekbox/geekbox.c create mode 100644 configs/geekbox_defconfig create mode 100644 include/configs/geekbox.h create mode 100644 include/configs/rk3368_common.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f9fddad..4ff1a26 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -838,14 +838,10 @@ config STM32 config ARCH_ROCKCHIP bool "Support Rockchip SoCs" - select SUPPORT_SPL - select SPL select OF_CONTROL select BLK select DM - select SPL_DM select SYS_MALLOC_F - select SPL_SYS_MALLOC_SIMPLE select DM_GPIO select DM_I2C select DM_MMC diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index 8b4a7c9..3ab7edc 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -609,6 +609,7 @@ uart2: serial at ff690000 { compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; reg = <0x0 0xff690000 0x0 0x100>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 86b77f8..597f043 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -3,6 +3,10 @@ if ARCH_ROCKCHIP config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7 + select SUPPORT_SPL + select SPL + select SPL_DM + select SPL_SYS_MALLOC_SIMPLE help The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two @@ -13,12 +17,21 @@ config ROCKCHIP_RK3288 config ROCKCHIP_RK3036 bool "Support Rockchip RK3036" select CPU_V7 + select SUPPORT_SPL + select SPL + select SPL_DM + select SPL_SYS_MALLOC_SIMPLE help The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3368 + bool "Support Rockchip RK3368" + select ARM64 + select SYS_NS16550 + config ROCKCHIP_SPL_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 @@ -29,4 +42,5 @@ config ROCKCHIP_SPL_BACK_TO_BROM source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3368/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 6763af4..48e78c1 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -16,3 +16,4 @@ obj-y += rk_timer.o endif obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig new file mode 100644 index 0000000..5f2cd53 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -0,0 +1,14 @@ +if ROCKCHIP_RK3368 + +config TARGET_GEEKBOX + bool "GeekBox" + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +source "board/geekbuying/geekbox/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile new file mode 100644 index 0000000..3e20498 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2016 Andreas F?rber +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rk3368.o diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c new file mode 100644 index 0000000..dd34fed --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2016 Andreas F?rber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region rk3368_mem_map[] = { + { + .base = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .base = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3368_mem_map; diff --git a/board/geekbuying/geekbox/Kconfig b/board/geekbuying/geekbox/Kconfig new file mode 100644 index 0000000..41aa8fb --- /dev/null +++ b/board/geekbuying/geekbox/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GEEKBOX + +config SYS_BOARD + default "geekbox" + +config SYS_VENDOR + default "geekbuying" + +config SYS_CONFIG_NAME + default "geekbox" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/geekbuying/geekbox/Makefile b/board/geekbuying/geekbox/Makefile new file mode 100644 index 0000000..5c1d66c --- /dev/null +++ b/board/geekbuying/geekbox/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2016 Andreas F?rber +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += geekbox.o diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c new file mode 100644 index 0000000..4a9c4ff --- /dev/null +++ b/board/geekbuying/geekbox/geekbox.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2016 Andreas F?rber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = 0x80000000; +} diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig new file mode 100644 index 0000000..6e82c22 --- /dev/null +++ b/configs/geekbox_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3368=y +CONFIG_TARGET_GEEKBOX=y +CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox" +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_IMLS is not set +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_SYSRESET=y +CONFIG_PINCTRL=y +CONFIG_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xFF690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/geekbox.h b/include/configs/geekbox.h new file mode 100644 index 0000000..47490f1 --- /dev/null +++ b/include/configs/geekbox.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016 Andreas F?rber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIGS_GEEKBOX_H +#define __CONFIGS_GEEKBOX_H + +#include <configs/rk3368_common.h> + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h new file mode 100644 index 0000000..27ff1b9 --- /dev/null +++ b/include/configs/rk3368_common.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016 Andreas F?rber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3368_COMMON_H +#define __CONFIG_RK3368_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include <asm/arch/hardware.h> +#include <linux/sizes.h> + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DISPLAY_BOARDINFO + +//#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_MEM32 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x00200000 +#endif +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#ifndef CONFIG_SPL_BUILD + +#include <config_distro_defaults.h> + +#define BOOT_TARGET_DEVICES(func) + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV + +#endif + +#endif -- 2.6.6 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox 2016-07-18 1:06 ` [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox Andreas Färber @ 2016-07-18 1:22 ` Andreas Färber 2016-07-18 11:56 ` Simon Glass 2016-07-18 12:13 ` Heiko Stübner 2 siblings, 0 replies; 17+ messages in thread From: Andreas Färber @ 2016-07-18 1:22 UTC (permalink / raw) To: u-boot Am 18.07.2016 um 03:06 schrieb Andreas F?rber: > The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. > > The GeekBox is a TV box from GeekBuying, based on an MXM3 module. > The module can be used with base boards such as the GeekBox Landingship. > > This adds basic support to chain-load U-Boot from Rockchip's miniloader. > > $ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img > # ./utils/upgrade_tool di uboot u-boot.img > > Implemented is the serial console, but no boot media drivers yet. > > Note that flashing the resulting U-Boot will not allow you to enter the > rockusb mode any more via "Update" button. Instead, you will need to > short two pins on the bottom of the module to enter MaskRom mode and > re-flash the loader: > > # ./utils/upgrade_tool ul ./lollipop_u-boot/RK3368MiniLoaderAll_V2.40.bin > # ./utils/upgrade_tool di uboot u-boot.img > > Signed-off-by: Andreas F?rber <afaerber@suse.de> > --- > arch/arm/Kconfig | 4 --- > arch/arm/dts/rk3368.dtsi | 1 + > arch/arm/mach-rockchip/Kconfig | 14 ++++++++++ > arch/arm/mach-rockchip/Makefile | 1 + > arch/arm/mach-rockchip/rk3368/Kconfig | 14 ++++++++++ > arch/arm/mach-rockchip/rk3368/Makefile | 7 +++++ > arch/arm/mach-rockchip/rk3368/rk3368.c | 28 ++++++++++++++++++++ > board/geekbuying/geekbox/Kconfig | 15 +++++++++++ > board/geekbuying/geekbox/Makefile | 7 +++++ > board/geekbuying/geekbox/geekbox.c | 26 +++++++++++++++++++ > configs/geekbox_defconfig | 20 +++++++++++++++ > include/configs/geekbox.h | 19 ++++++++++++++ > include/configs/rk3368_common.h | 47 ++++++++++++++++++++++++++++++++++ > 13 files changed, 199 insertions(+), 4 deletions(-) > create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig > create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile > create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c > create mode 100644 board/geekbuying/geekbox/Kconfig > create mode 100644 board/geekbuying/geekbox/Makefile > create mode 100644 board/geekbuying/geekbox/geekbox.c > create mode 100644 configs/geekbox_defconfig > create mode 100644 include/configs/geekbox.h > create mode 100644 include/configs/rk3368_common.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index f9fddad..4ff1a26 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -838,14 +838,10 @@ config STM32 > > config ARCH_ROCKCHIP > bool "Support Rockchip SoCs" > - select SUPPORT_SPL > - select SPL > select OF_CONTROL > select BLK > select DM > - select SPL_DM > select SYS_MALLOC_F > - select SPL_SYS_MALLOC_SIMPLE > select DM_GPIO > select DM_I2C > select DM_MMC > diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi > index 8b4a7c9..3ab7edc 100644 > --- a/arch/arm/dts/rk3368.dtsi > +++ b/arch/arm/dts/rk3368.dtsi > @@ -609,6 +609,7 @@ > uart2: serial at ff690000 { > compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; > reg = <0x0 0xff690000 0x0 0x100>; > + clock-frequency = <24000000>; > clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; > clock-names = "baudclk", "apb_pclk"; > interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig > index 86b77f8..597f043 100644 > --- a/arch/arm/mach-rockchip/Kconfig > +++ b/arch/arm/mach-rockchip/Kconfig > @@ -3,6 +3,10 @@ if ARCH_ROCKCHIP > config ROCKCHIP_RK3288 > bool "Support Rockchip RK3288" > select CPU_V7 > + select SUPPORT_SPL > + select SPL > + select SPL_DM > + select SPL_SYS_MALLOC_SIMPLE > help > The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 > including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two > @@ -13,12 +17,21 @@ config ROCKCHIP_RK3288 > config ROCKCHIP_RK3036 > bool "Support Rockchip RK3036" > select CPU_V7 > + select SUPPORT_SPL > + select SPL > + select SPL_DM > + select SPL_SYS_MALLOC_SIMPLE > help > The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 > including NEON and GPU, Mali-400 graphics, several DDR3 options > and video codec support. Peripherals include Gigabit Ethernet, > USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. > > +config ROCKCHIP_RK3368 > + bool "Support Rockchip RK3368" > + select ARM64 > + select SYS_NS16550 > + > config ROCKCHIP_SPL_BACK_TO_BROM > bool "SPL returns to bootrom" > default y if ROCKCHIP_RK3036 > @@ -29,4 +42,5 @@ config ROCKCHIP_SPL_BACK_TO_BROM > > source "arch/arm/mach-rockchip/rk3288/Kconfig" > source "arch/arm/mach-rockchip/rk3036/Kconfig" > +source "arch/arm/mach-rockchip/rk3368/Kconfig" > endif > diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile > index 6763af4..48e78c1 100644 > --- a/arch/arm/mach-rockchip/Makefile > +++ b/arch/arm/mach-rockchip/Makefile > @@ -16,3 +16,4 @@ obj-y += rk_timer.o > endif > obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ > obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ > +obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ > diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig > new file mode 100644 > index 0000000..5f2cd53 > --- /dev/null > +++ b/arch/arm/mach-rockchip/rk3368/Kconfig > @@ -0,0 +1,14 @@ > +if ROCKCHIP_RK3368 > + > +config TARGET_GEEKBOX > + bool "GeekBox" > + > +config SYS_SOC > + default "rockchip" > + > +config SYS_MALLOC_F_LEN > + default 0x0800 > + > +source "board/geekbuying/geekbox/Kconfig" > + > +endif > diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile > new file mode 100644 > index 0000000..3e20498 > --- /dev/null > +++ b/arch/arm/mach-rockchip/rk3368/Makefile > @@ -0,0 +1,7 @@ > +# > +# Copyright (c) 2016 Andreas F?rber > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += rk3368.o > diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c > new file mode 100644 > index 0000000..dd34fed > --- /dev/null > +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c > @@ -0,0 +1,28 @@ > +/* > + * Copyright (c) 2016 Andreas F?rber Copied from rk3399, should reproduce Rockchip copyright. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/armv8/mmu.h> > + > +static struct mm_region rk3368_mem_map[] = { > + { > + .base = 0x0UL, > + .size = 0x80000000UL, > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | > + PTE_BLOCK_INNER_SHARE > + }, { > + .base = 0xf0000000UL, > + .size = 0x10000000UL, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* List terminator */ > + 0, > + } > +}; > + > +struct mm_region *mem_map = rk3368_mem_map; > diff --git a/board/geekbuying/geekbox/Kconfig b/board/geekbuying/geekbox/Kconfig > new file mode 100644 > index 0000000..41aa8fb > --- /dev/null > +++ b/board/geekbuying/geekbox/Kconfig > @@ -0,0 +1,15 @@ > +if TARGET_GEEKBOX > + > +config SYS_BOARD > + default "geekbox" > + > +config SYS_VENDOR > + default "geekbuying" > + > +config SYS_CONFIG_NAME > + default "geekbox" > + > +config BOARD_SPECIFIC_OPTIONS # dummy > + def_bool y > + > +endif > diff --git a/board/geekbuying/geekbox/Makefile b/board/geekbuying/geekbox/Makefile > new file mode 100644 > index 0000000..5c1d66c > --- /dev/null > +++ b/board/geekbuying/geekbox/Makefile > @@ -0,0 +1,7 @@ > +# > +# Copyright (c) 2016 Andreas F?rber > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += geekbox.o > diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c > new file mode 100644 > index 0000000..4a9c4ff > --- /dev/null > +++ b/board/geekbuying/geekbox/geekbox.c > @@ -0,0 +1,26 @@ > +/* > + * Copyright (c) 2016 Andreas F?rber > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int board_init(void) > +{ > + return 0; > +} > + > +int dram_init(void) > +{ > + gd->ram_size = 0x80000000; > + return 0; > +} > + > +void dram_init_banksize(void) > +{ > + gd->bd->bi_dram[0].start = 0; > + gd->bd->bi_dram[0].size = 0x80000000; > +} > diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig > new file mode 100644 > index 0000000..6e82c22 > --- /dev/null > +++ b/configs/geekbox_defconfig > @@ -0,0 +1,20 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_ROCKCHIP_RK3368=y > +CONFIG_TARGET_GEEKBOX=y > +CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox" > +CONFIG_HUSH_PARSER=y > +# CONFIG_CMD_IMLS is not set > +CONFIG_REGMAP=y > +CONFIG_SYSCON=y > +CONFIG_CLK=y > +CONFIG_SYSRESET=y > +CONFIG_PINCTRL=y > +CONFIG_RAM=y Not all of these may actually be necessary? Ditto for rk3399. > +CONFIG_DEBUG_UART=y > +CONFIG_DEBUG_UART_BASE=0xFF690000 > +CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_DEBUG_UART_ANNOUNCE=y This one didn't work and should be dropped anyway. > +CONFIG_DEBUG_UART_SKIP_INIT=y > +CONFIG_ERRNO_STR=y > diff --git a/include/configs/geekbox.h b/include/configs/geekbox.h > new file mode 100644 > index 0000000..47490f1 > --- /dev/null > +++ b/include/configs/geekbox.h > @@ -0,0 +1,19 @@ > +/* > + * Copyright (c) 2016 Andreas F?rber > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __CONFIGS_GEEKBOX_H > +#define __CONFIGS_GEEKBOX_H > + > +#include <configs/rk3368_common.h> > + > +#define CONFIG_ENV_IS_NOWHERE > +#define CONFIG_ENV_SIZE 0x2000 > +#define CONFIG_SYS_NO_FLASH > + > +#define CONFIG_SYS_WHITE_ON_BLACK > +#define CONFIG_CONSOLE_SCROLL_LINES 10 > + > +#endif > diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h > new file mode 100644 > index 0000000..27ff1b9 > --- /dev/null > +++ b/include/configs/rk3368_common.h > @@ -0,0 +1,47 @@ > +/* > + * Copyright (c) 2016 Andreas F?rber > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __CONFIG_RK3368_COMMON_H > +#define __CONFIG_RK3368_COMMON_H > + > +#define CONFIG_SYS_CACHELINE_SIZE 64 > + > +#include <asm/arch/hardware.h> > +#include <linux/sizes.h> > + > +#define CONFIG_NR_DRAM_BANKS 1 > +#define CONFIG_SYS_MAXARGS 16 > +#define CONFIG_BAUDRATE 115200 > +#define CONFIG_SYS_MALLOC_LEN (32 << 20) > +#define CONFIG_SYS_CBSIZE 1024 > +#define CONFIG_SKIP_LOWLEVEL_INIT > +#define CONFIG_DISPLAY_BOARDINFO > + > +//#define CONFIG_SYS_NS16550 Leftover, replaced by Kconfig. > +#define CONFIG_SYS_NS16550_MEM32 > + > +#ifdef CONFIG_SPL_BUILD > +#define CONFIG_SYS_TEXT_BASE 0x00000000 > +#else > +#define CONFIG_SYS_TEXT_BASE 0x00200000 > +#endif > +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 > +#define CONFIG_SYS_LOAD_ADDR 0x00800800 > + > +#ifndef CONFIG_SPL_BUILD > + > +#include <config_distro_defaults.h> > + > +#define BOOT_TARGET_DEVICES(func) > + > +#include <config_distro_bootcmd.h> > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + BOOTENV > + > +#endif > + > +#endif Regards, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany GF: Felix Imend?rffer, Jane Smithard, Graham Norton HRB 21284 (AG N?rnberg) ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox 2016-07-18 1:06 ` [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox Andreas Färber 2016-07-18 1:22 ` Andreas Färber @ 2016-07-18 11:56 ` Simon Glass 2016-07-18 12:13 ` Heiko Stübner 2 siblings, 0 replies; 17+ messages in thread From: Simon Glass @ 2016-07-18 11:56 UTC (permalink / raw) To: u-boot Hi Andreas, On 17 July 2016 at 19:06, Andreas F?rber <afaerber@suse.de> wrote: > The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. > > The GeekBox is a TV box from GeekBuying, based on an MXM3 module. > The module can be used with base boards such as the GeekBox Landingship. > > This adds basic support to chain-load U-Boot from Rockchip's miniloader. > > $ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img > # ./utils/upgrade_tool di uboot u-boot.img > > Implemented is the serial console, but no boot media drivers yet. > > Note that flashing the resulting U-Boot will not allow you to enter the > rockusb mode any more via "Update" button. Instead, you will need to > short two pins on the bottom of the module to enter MaskRom mode and > re-flash the loader: > > # ./utils/upgrade_tool ul ./lollipop_u-boot/RK3368MiniLoaderAll_V2.40.bin > # ./utils/upgrade_tool di uboot u-boot.img > > Signed-off-by: Andreas F?rber <afaerber@suse.de> > --- > arch/arm/Kconfig | 4 --- > arch/arm/dts/rk3368.dtsi | 1 + > arch/arm/mach-rockchip/Kconfig | 14 ++++++++++ > arch/arm/mach-rockchip/Makefile | 1 + > arch/arm/mach-rockchip/rk3368/Kconfig | 14 ++++++++++ > arch/arm/mach-rockchip/rk3368/Makefile | 7 +++++ > arch/arm/mach-rockchip/rk3368/rk3368.c | 28 ++++++++++++++++++++ > board/geekbuying/geekbox/Kconfig | 15 +++++++++++ > board/geekbuying/geekbox/Makefile | 7 +++++ > board/geekbuying/geekbox/geekbox.c | 26 +++++++++++++++++++ > configs/geekbox_defconfig | 20 +++++++++++++++ > include/configs/geekbox.h | 19 ++++++++++++++ > include/configs/rk3368_common.h | 47 ++++++++++++++++++++++++++++++++++ > 13 files changed, 199 insertions(+), 4 deletions(-) > create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig > create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile > create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c > create mode 100644 board/geekbuying/geekbox/Kconfig > create mode 100644 board/geekbuying/geekbox/Makefile > create mode 100644 board/geekbuying/geekbox/geekbox.c > create mode 100644 configs/geekbox_defconfig > create mode 100644 include/configs/geekbox.h > create mode 100644 include/configs/rk3368_common.h Acked-by: Simon Glass <sjg@chromium.org> Can you please also send a README in board/geekbuying/geekbox with the flashing info from your cover letter? Regards, Simon ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox 2016-07-18 1:06 ` [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox Andreas Färber 2016-07-18 1:22 ` Andreas Färber 2016-07-18 11:56 ` Simon Glass @ 2016-07-18 12:13 ` Heiko Stübner 2016-07-23 2:31 ` Simon Glass 2 siblings, 1 reply; 17+ messages in thread From: Heiko Stübner @ 2016-07-18 12:13 UTC (permalink / raw) To: u-boot Hi Andreas, Am Montag, 18. Juli 2016, 03:06:07 schrieb Andreas F?rber: > The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. > > The GeekBox is a TV box from GeekBuying, based on an MXM3 module. > The module can be used with base boards such as the GeekBox Landingship. > > This adds basic support to chain-load U-Boot from Rockchip's miniloader. > > $ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img > # ./utils/upgrade_tool di uboot u-boot.img > > Implemented is the serial console, but no boot media drivers yet. > > Note that flashing the resulting U-Boot will not allow you to enter the > rockusb mode any more via "Update" button. Instead, you will need to > short two pins on the bottom of the module to enter MaskRom mode and > re-flash the loader: > > # ./utils/upgrade_tool ul ./lollipop_u-boot/RK3368MiniLoaderAll_V2.40.bin > # ./utils/upgrade_tool di uboot u-boot.img > > Signed-off-by: Andreas F?rber <afaerber@suse.de> > --- > arch/arm/Kconfig | 4 --- > arch/arm/dts/rk3368.dtsi | 1 + > arch/arm/mach-rockchip/Kconfig | 14 ++++++++++ > arch/arm/mach-rockchip/Makefile | 1 + > arch/arm/mach-rockchip/rk3368/Kconfig | 14 ++++++++++ > arch/arm/mach-rockchip/rk3368/Makefile | 7 +++++ > arch/arm/mach-rockchip/rk3368/rk3368.c | 28 ++++++++++++++++++++ > board/geekbuying/geekbox/Kconfig | 15 +++++++++++ > board/geekbuying/geekbox/Makefile | 7 +++++ > board/geekbuying/geekbox/geekbox.c | 26 +++++++++++++++++++ > configs/geekbox_defconfig | 20 +++++++++++++++ > include/configs/geekbox.h | 19 ++++++++++++++ > include/configs/rk3368_common.h | 47 > ++++++++++++++++++++++++++++++++++ 13 files changed, 199 insertions(+), 4 > deletions(-) > create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig > create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile > create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c > create mode 100644 board/geekbuying/geekbox/Kconfig > create mode 100644 board/geekbuying/geekbox/Makefile > create mode 100644 board/geekbuying/geekbox/geekbox.c > create mode 100644 configs/geekbox_defconfig > create mode 100644 include/configs/geekbox.h > create mode 100644 include/configs/rk3368_common.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index f9fddad..4ff1a26 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -838,14 +838,10 @@ config STM32 > > config ARCH_ROCKCHIP > bool "Support Rockchip SoCs" > - select SUPPORT_SPL > - select SPL > select OF_CONTROL > select BLK > select DM > - select SPL_DM > select SYS_MALLOC_F > - select SPL_SYS_MALLOC_SIMPLE > select DM_GPIO > select DM_I2C > select DM_MMC [...] > diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig > index 86b77f8..597f043 100644 > --- a/arch/arm/mach-rockchip/Kconfig > +++ b/arch/arm/mach-rockchip/Kconfig > @@ -3,6 +3,10 @@ if ARCH_ROCKCHIP > config ROCKCHIP_RK3288 > bool "Support Rockchip RK3288" > select CPU_V7 > + select SUPPORT_SPL > + select SPL > + select SPL_DM > + select SPL_SYS_MALLOC_SIMPLE > help > The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 > including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two > @@ -13,12 +17,21 @@ config ROCKCHIP_RK3288 > config ROCKCHIP_RK3036 > bool "Support Rockchip RK3036" > select CPU_V7 > + select SUPPORT_SPL > + select SPL > + select SPL_DM > + select SPL_SYS_MALLOC_SIMPLE > help > The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 > including NEON and GPU, Mali-400 graphics, several DDR3 options > and video codec support. Peripherals include Gigabit Ethernet, > USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. looks like both you and Kever need that separation of the SPL symbols (me as well for the rk3188 for the time being), so it might make sense to split that out into a separate patch, all could use. I guess it might also make it easier for Simon to find an order to apply the patches? Heiko ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox 2016-07-18 12:13 ` Heiko Stübner @ 2016-07-23 2:31 ` Simon Glass 2016-07-25 14:46 ` Andreas Färber 0 siblings, 1 reply; 17+ messages in thread From: Simon Glass @ 2016-07-23 2:31 UTC (permalink / raw) To: u-boot Hi, On 18 July 2016 at 06:13, Heiko St?bner <heiko@sntech.de> wrote: > Hi Andreas, > > Am Montag, 18. Juli 2016, 03:06:07 schrieb Andreas F?rber: >> The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. >> >> The GeekBox is a TV box from GeekBuying, based on an MXM3 module. >> The module can be used with base boards such as the GeekBox Landingship. >> >> This adds basic support to chain-load U-Boot from Rockchip's miniloader. >> >> $ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img >> # ./utils/upgrade_tool di uboot u-boot.img >> >> Implemented is the serial console, but no boot media drivers yet. >> >> Note that flashing the resulting U-Boot will not allow you to enter the >> rockusb mode any more via "Update" button. Instead, you will need to >> short two pins on the bottom of the module to enter MaskRom mode and >> re-flash the loader: >> >> # ./utils/upgrade_tool ul ./lollipop_u-boot/RK3368MiniLoaderAll_V2.40.bin >> # ./utils/upgrade_tool di uboot u-boot.img >> >> Signed-off-by: Andreas F?rber <afaerber@suse.de> >> --- >> arch/arm/Kconfig | 4 --- >> arch/arm/dts/rk3368.dtsi | 1 + >> arch/arm/mach-rockchip/Kconfig | 14 ++++++++++ >> arch/arm/mach-rockchip/Makefile | 1 + >> arch/arm/mach-rockchip/rk3368/Kconfig | 14 ++++++++++ >> arch/arm/mach-rockchip/rk3368/Makefile | 7 +++++ >> arch/arm/mach-rockchip/rk3368/rk3368.c | 28 ++++++++++++++++++++ >> board/geekbuying/geekbox/Kconfig | 15 +++++++++++ >> board/geekbuying/geekbox/Makefile | 7 +++++ >> board/geekbuying/geekbox/geekbox.c | 26 +++++++++++++++++++ >> configs/geekbox_defconfig | 20 +++++++++++++++ >> include/configs/geekbox.h | 19 ++++++++++++++ >> include/configs/rk3368_common.h | 47 >> ++++++++++++++++++++++++++++++++++ 13 files changed, 199 insertions(+), 4 >> deletions(-) >> create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig >> create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile >> create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c >> create mode 100644 board/geekbuying/geekbox/Kconfig >> create mode 100644 board/geekbuying/geekbox/Makefile >> create mode 100644 board/geekbuying/geekbox/geekbox.c >> create mode 100644 configs/geekbox_defconfig >> create mode 100644 include/configs/geekbox.h >> create mode 100644 include/configs/rk3368_common.h >> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >> index f9fddad..4ff1a26 100644 >> --- a/arch/arm/Kconfig >> +++ b/arch/arm/Kconfig >> @@ -838,14 +838,10 @@ config STM32 >> >> config ARCH_ROCKCHIP >> bool "Support Rockchip SoCs" >> - select SUPPORT_SPL >> - select SPL >> select OF_CONTROL >> select BLK >> select DM >> - select SPL_DM >> select SYS_MALLOC_F >> - select SPL_SYS_MALLOC_SIMPLE >> select DM_GPIO >> select DM_I2C >> select DM_MMC > [...] >> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig >> index 86b77f8..597f043 100644 >> --- a/arch/arm/mach-rockchip/Kconfig >> +++ b/arch/arm/mach-rockchip/Kconfig >> @@ -3,6 +3,10 @@ if ARCH_ROCKCHIP >> config ROCKCHIP_RK3288 >> bool "Support Rockchip RK3288" >> select CPU_V7 >> + select SUPPORT_SPL >> + select SPL >> + select SPL_DM >> + select SPL_SYS_MALLOC_SIMPLE >> help >> The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 >> including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two >> @@ -13,12 +17,21 @@ config ROCKCHIP_RK3288 >> config ROCKCHIP_RK3036 >> bool "Support Rockchip RK3036" >> select CPU_V7 >> + select SUPPORT_SPL >> + select SPL >> + select SPL_DM >> + select SPL_SYS_MALLOC_SIMPLE >> help >> The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 >> including NEON and GPU, Mali-400 graphics, several DDR3 options >> and video codec support. Peripherals include Gigabit Ethernet, >> USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. > > looks like both you and Kever need that separation of the SPL symbols (me as > well for the rk3188 for the time being), so it might make sense to split that > out into a separate patch, all could use. > > I guess it might also make it easier for Simon to find an order to apply the > patches? Yes. Andreas, can you please resent your patches against u-boot-rockchip/master? Also it needs a MAINTAINERS file I think. Regards, Simon ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox 2016-07-23 2:31 ` Simon Glass @ 2016-07-25 14:46 ` Andreas Färber 0 siblings, 0 replies; 17+ messages in thread From: Andreas Färber @ 2016-07-25 14:46 UTC (permalink / raw) To: u-boot Hi Simon, Am 23.07.2016 um 04:31 schrieb Simon Glass: > On 18 July 2016 at 06:13, Heiko St?bner <heiko@sntech.de> wrote: >> Am Montag, 18. Juli 2016, 03:06:07 schrieb Andreas F?rber: >>> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig >>> index 86b77f8..597f043 100644 >>> --- a/arch/arm/mach-rockchip/Kconfig >>> +++ b/arch/arm/mach-rockchip/Kconfig >>> @@ -3,6 +3,10 @@ if ARCH_ROCKCHIP >>> config ROCKCHIP_RK3288 >>> bool "Support Rockchip RK3288" >>> select CPU_V7 >>> + select SUPPORT_SPL >>> + select SPL >>> + select SPL_DM >>> + select SPL_SYS_MALLOC_SIMPLE >>> help >>> The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 >>> including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two >>> @@ -13,12 +17,21 @@ config ROCKCHIP_RK3288 >>> config ROCKCHIP_RK3036 >>> bool "Support Rockchip RK3036" >>> select CPU_V7 >>> + select SUPPORT_SPL >>> + select SPL >>> + select SPL_DM >>> + select SPL_SYS_MALLOC_SIMPLE >>> help >>> The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 >>> including NEON and GPU, Mali-400 graphics, several DDR3 options >>> and video codec support. Peripherals include Gigabit Ethernet, >>> USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. >> >> looks like both you and Kever need that separation of the SPL symbols (me as >> well for the rk3188 for the time being), so it might make sense to split that >> out into a separate patch, all could use. >> >> I guess it might also make it easier for Simon to find an order to apply the >> patches? > > Yes. Andreas, can you please resent your patches against u-boot-rockchip/master? I had done that and thereby ran into the mismerges I pointed out. ;) Didn't send that blown-up version out since you suggested an rk3399 resend, which came once I was unavailable over the extended weekend... > Also it needs a MAINTAINERS file I think. True. Regards, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany GF: Felix Imend?rffer, Jane Smithard, Graham Norton HRB 21284 (AG N?rnberg) ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support 2016-07-18 1:06 [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support Andreas Färber 2016-07-18 1:06 ` [U-Boot] [PATCH 1/2] dts: Import rk3368-geekbox.dts Andreas Färber 2016-07-18 1:06 ` [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox Andreas Färber @ 2016-08-06 4:30 ` Simon Glass 2016-08-06 16:05 ` Andreas Färber 2016-08-29 7:17 ` Peter Robinson 3 siblings, 1 reply; 17+ messages in thread From: Simon Glass @ 2016-08-06 4:30 UTC (permalink / raw) To: u-boot Hi Andreas, On 17 July 2016 at 19:06, Andreas F?rber <afaerber@suse.de> wrote: > Hi, > > This series adds initial support for RK3368 SoC and GeekBox. > For more details see the commit message. > > Will need to be rebased onto Heiko's cleanups and Kever's RK3399 series. > > Regards, > Andreas > > Cc: Simon Glass <sjg@chromium.org> > Cc: Kever Yang <kever.yang@rock-chips.com> > Cc: Heiko St?bner <heiko@sntech.de> > > Andreas F?rber (2): > dts: Import rk3368-geekbox.dts > ARM64: rockchip: Add initial support for RK3368 based GeekBox > Are you planning to respin these patches? I'd like to get them applied soon. Thanks, Simon > arch/arm/Kconfig | 4 - > arch/arm/dts/Makefile | 3 +- > arch/arm/dts/rk3368-geekbox.dts | 319 ++++++++++ > arch/arm/dts/rk3368.dtsi | 1082 ++++++++++++++++++++++++++++++++ > arch/arm/mach-rockchip/Kconfig | 14 + > arch/arm/mach-rockchip/Makefile | 1 + > arch/arm/mach-rockchip/rk3368/Kconfig | 14 + > arch/arm/mach-rockchip/rk3368/Makefile | 7 + > arch/arm/mach-rockchip/rk3368/rk3368.c | 28 + > board/geekbuying/geekbox/Kconfig | 15 + > board/geekbuying/geekbox/Makefile | 7 + > board/geekbuying/geekbox/geekbox.c | 26 + > configs/geekbox_defconfig | 20 + > include/configs/geekbox.h | 19 + > include/configs/rk3368_common.h | 47 ++ > include/dt-bindings/clock/rk3368-cru.h | 384 ++++++++++++ > 16 files changed, 1985 insertions(+), 5 deletions(-) > create mode 100644 arch/arm/dts/rk3368-geekbox.dts > create mode 100644 arch/arm/dts/rk3368.dtsi > create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig > create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile > create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c > create mode 100644 board/geekbuying/geekbox/Kconfig > create mode 100644 board/geekbuying/geekbox/Makefile > create mode 100644 board/geekbuying/geekbox/geekbox.c > create mode 100644 configs/geekbox_defconfig > create mode 100644 include/configs/geekbox.h > create mode 100644 include/configs/rk3368_common.h > create mode 100644 include/dt-bindings/clock/rk3368-cru.h > > -- > 2.6.6 > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support 2016-08-06 4:30 ` [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support Simon Glass @ 2016-08-06 16:05 ` Andreas Färber 2016-08-06 18:52 ` Simon Glass 2016-08-07 13:31 ` Tom Rini 0 siblings, 2 replies; 17+ messages in thread From: Andreas Färber @ 2016-08-06 16:05 UTC (permalink / raw) To: u-boot Hi Simon, Am 06.08.2016 um 06:30 schrieb Simon Glass: > Hi Andreas, > > On 17 July 2016 at 19:06, Andreas F?rber <afaerber@suse.de> wrote: >> Hi, >> >> This series adds initial support for RK3368 SoC and GeekBox. >> For more details see the commit message. >> >> Will need to be rebased onto Heiko's cleanups and Kever's RK3399 series. >> >> Regards, >> Andreas >> >> Cc: Simon Glass <sjg@chromium.org> >> Cc: Kever Yang <kever.yang@rock-chips.com> >> Cc: Heiko St?bner <heiko@sntech.de> >> >> Andreas F?rber (2): >> dts: Import rk3368-geekbox.dts >> ARM64: rockchip: Add initial support for RK3368 based GeekBox >> > > Are you planning to respin these patches? Eventually...? > I'd like to get them applied soon. And I'd like to get my work recognized! However, despite our previous IRC chat, I had to find out _while_ replying to the rk3399 mails that you had once again not just applied all patches (twenty minutes after ack'ing them on a Saturday) but already sent a pull on Tuesday my nighttime that I was not CC'ed on and that Tom has merged the night after. So it feels like I'm wasting my time here and consequently I stopped my review and rebase. Not only that it's too late for the patches themselves, but Wolfgang also publishes statistics of Reviewed-bys, which we can't add to commits after merging. If you as maintainer don't give people who spent time providing serious review comments sufficient chance to add their Reviewed-by - and a weekend of absence is certainly something to cope with since you said you were away end of that week as well - it becomes a distorted, non-telling statistic. So I am kindly suggesting that Wolfgang drops the Reviewed-by statistics if maintainers don't care for them and instead we just all do ugly fix-ups so that we can at least get recognition in the Signed-off-by statistics. While we're only talking about 4 tags here, it's a matter of principle and respect. Thanks, Andreas > > Thanks, > Simon [snip] -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany GF: Felix Imend?rffer, Jane Smithard, Graham Norton HRB 21284 (AG N?rnberg) ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support 2016-08-06 16:05 ` Andreas Färber @ 2016-08-06 18:52 ` Simon Glass 2016-08-07 13:31 ` Tom Rini 1 sibling, 0 replies; 17+ messages in thread From: Simon Glass @ 2016-08-06 18:52 UTC (permalink / raw) To: u-boot +Tom for comment Hi Andreas, On 6 August 2016 at 10:05, Andreas F?rber <afaerber@suse.de> wrote: > Hi Simon, > > Am 06.08.2016 um 06:30 schrieb Simon Glass: >> Hi Andreas, >> >> On 17 July 2016 at 19:06, Andreas F?rber <afaerber@suse.de> wrote: >>> Hi, >>> >>> This series adds initial support for RK3368 SoC and GeekBox. >>> For more details see the commit message. >>> >>> Will need to be rebased onto Heiko's cleanups and Kever's RK3399 series. >>> >>> Regards, >>> Andreas >>> >>> Cc: Simon Glass <sjg@chromium.org> >>> Cc: Kever Yang <kever.yang@rock-chips.com> >>> Cc: Heiko St?bner <heiko@sntech.de> >>> >>> Andreas F?rber (2): >>> dts: Import rk3368-geekbox.dts >>> ARM64: rockchip: Add initial support for RK3368 based GeekBox >>> >> >> Are you planning to respin these patches? > > Eventually...? If it is soon then I can get this in for the upcoming release. Otherwise I'll need to wait. Also can you please add a README with a bit more detail on how to test it? Your cover letter suggests that it requires shorting two pins (which pins?) after flashing U-Boot. Is there another way for me to try it? > >> I'd like to get them applied soon. > > And I'd like to get my work recognized! However, despite our previous > IRC chat, I had to find out _while_ replying to the rk3399 mails that > you had once again not just applied all patches (twenty minutes after > ack'ing them on a Saturday) but already sent a pull on Tuesday my > nighttime that I was not CC'ed on and that Tom has merged the night > after. So it feels like I'm wasting my time here and consequently I > stopped my review and rebase. > > Not only that it's too late for the patches themselves, but Wolfgang > also publishes statistics of Reviewed-bys, which we can't add to commits > after merging. If you as maintainer don't give people who spent time > providing serious review comments sufficient chance to add their > Reviewed-by - and a weekend of absence is certainly something to cope > with since you said you were away end of that week as well - it becomes > a distorted, non-telling statistic. So I am kindly suggesting that > Wolfgang drops the Reviewed-by statistics if maintainers don't care for > them and instead we just all do ugly fix-ups so that we can at least get > recognition in the Signed-off-by statistics. > > While we're only talking about 4 tags here, it's a matter of principle > and respect. What do you mean by respect? I normally expect a follow-up review to come through fairly quickly. The last review I saw from you was 10 days ago. I tend to want to move things forward fairly quickly in general for Rockchip, but particularly at this point where the merge window is closed and pending patches really need to get in for testing. So a few questions: - How long do you expect a patch to sit on the list before I pick it up? - Similarly for a follow-up v2, etc. patch? - How long between my Ack and applying? - Anything else you are looking for? I seldom copy people on the pull requests - is that something we should be doing? I'm happy to adjust the rules for Rockchip if it will encourage more participation. This is very new in mainline so there is a lot to do. > > Thanks, > Andreas Regards, Simon ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support 2016-08-06 16:05 ` Andreas Färber 2016-08-06 18:52 ` Simon Glass @ 2016-08-07 13:31 ` Tom Rini 2016-08-07 16:46 ` Andreas Färber 1 sibling, 1 reply; 17+ messages in thread From: Tom Rini @ 2016-08-07 13:31 UTC (permalink / raw) To: u-boot On Sat, Aug 06, 2016 at 06:05:29PM +0200, Andreas F?rber wrote: > Hi Simon, > > Am 06.08.2016 um 06:30 schrieb Simon Glass: > > Hi Andreas, > > > > On 17 July 2016 at 19:06, Andreas F?rber <afaerber@suse.de> wrote: > >> Hi, > >> > >> This series adds initial support for RK3368 SoC and GeekBox. > >> For more details see the commit message. > >> > >> Will need to be rebased onto Heiko's cleanups and Kever's RK3399 series. > >> > >> Regards, > >> Andreas > >> > >> Cc: Simon Glass <sjg@chromium.org> > >> Cc: Kever Yang <kever.yang@rock-chips.com> > >> Cc: Heiko St?bner <heiko@sntech.de> > >> > >> Andreas F?rber (2): > >> dts: Import rk3368-geekbox.dts > >> ARM64: rockchip: Add initial support for RK3368 based GeekBox > >> > > > > Are you planning to respin these patches? > > Eventually...? > > > I'd like to get them applied soon. > > And I'd like to get my work recognized! However, despite our previous > IRC chat, I had to find out _while_ replying to the rk3399 mails that > you had once again not just applied all patches (twenty minutes after > ack'ing them on a Saturday) but already sent a pull on Tuesday my > nighttime that I was not CC'ed on and that Tom has merged the night > after. So it feels like I'm wasting my time here and consequently I > stopped my review and rebase. In the U-Boot community, we are not in the habit of cc'ing everyone with a change in a given pull request. Is there a tool the kernel folks use here that makes this easy? And the rule of thumb that I use, and I try and get everyone else to use as well is that a patch should be out for a week before it gets picked up and merged as that should give everyone time to review, comment and test. Did that not happen with the patches Simon picked up? Thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160807/667e159b/attachment.sig> ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support 2016-08-07 13:31 ` Tom Rini @ 2016-08-07 16:46 ` Andreas Färber 2016-08-07 20:07 ` Tom Rini 0 siblings, 1 reply; 17+ messages in thread From: Andreas Färber @ 2016-08-07 16:46 UTC (permalink / raw) To: u-boot Am 07.08.2016 um 15:31 schrieb Tom Rini: > On Sat, Aug 06, 2016 at 06:05:29PM +0200, Andreas F?rber wrote: >> Hi Simon, >> >> Am 06.08.2016 um 06:30 schrieb Simon Glass: >>> Hi Andreas, >>> >>> On 17 July 2016 at 19:06, Andreas F?rber <afaerber@suse.de> wrote: >>>> Hi, >>>> >>>> This series adds initial support for RK3368 SoC and GeekBox. >>>> For more details see the commit message. >>>> >>>> Will need to be rebased onto Heiko's cleanups and Kever's RK3399 series. >>>> >>>> Regards, >>>> Andreas >>>> >>>> Cc: Simon Glass <sjg@chromium.org> >>>> Cc: Kever Yang <kever.yang@rock-chips.com> >>>> Cc: Heiko St?bner <heiko@sntech.de> >>>> >>>> Andreas F?rber (2): >>>> dts: Import rk3368-geekbox.dts >>>> ARM64: rockchip: Add initial support for RK3368 based GeekBox >>>> >>> >>> Are you planning to respin these patches? >> >> Eventually...? >> >>> I'd like to get them applied soon. >> >> And I'd like to get my work recognized! However, despite our previous >> IRC chat, I had to find out _while_ replying to the rk3399 mails that >> you had once again not just applied all patches (twenty minutes after >> ack'ing them on a Saturday) but already sent a pull on Tuesday my >> nighttime that I was not CC'ed on and that Tom has merged the night >> after. So it feels like I'm wasting my time here and consequently I >> stopped my review and rebase. > > In the U-Boot community, we are not in the habit of cc'ing everyone with > a change in a given pull request. Is there a tool the kernel folks use > here that makes this easy? Not that I'm aware of. But that is besides the point, as my very complaint is that I'm not credited in the patches that got merged, so no tool could've extracted my name for CC'ing. It's about Simon having mismerged those patches and having overlooked unresolved review comments of mine for those patches before and me specifically having complained to him about not waiting for my Reviewed-by before applying them. So him seeing that I did not reply to his Saturday mails, I feel it would've been fair in this particular case a) to ping me again after the weekend and b) to let me know that he is no longer waiting for my review comments or that I really need to hurry up with an objection until X. He did not say so in a reply that reached my inbox, and I was not CC'ed on the pull request itself, thus a pull request behind my back. I'm not too deep into U-Boot, so maybe there was a reason for this hush-hush workflow, but then at least the communication was fairly bad. Had I known that the pull is already on the list, I wouldn't have replied with a Reviewed-by for 1/4 that same day (which surely Simon was CC'ed on) or I could've asked Tom to hold off merging it until I'm done reviewing the next day. > And the rule of thumb that I use, and I try and get everyone else to use > as well is that a patch should be out for a week before it gets picked > up and merged as that should give everyone time to review, comment and > test. Did that not happen with the patches Simon picked up? Slightly less than a week. For some other projects it's ~two weeks. Also again note that this is not about some random patch but one where Simon specifically said he would be away, that he would exchange the patches on his branch where necessary and where he asked me to "sing". It leaves a bad taste that Simon was absent himself the week the patches were posted but apparently expects me to be available whenever he is. I don't work on U-Boot as a job, and for rebasing rk3368 patches - which many of my review comments resulted from - I need access to the hardware for testing. Note that I was similarly surprised how quickly two patches of mine went into his tree, with just one day in between and despite conflicts between my rk3368 and Kever's rk3399 preparations. I can see that having patches in a tree facilitates testing, but it also prevents serious peer review when not just staging but also merging them. Regards, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany GF: Felix Imend?rffer, Jane Smithard, Graham Norton HRB 21284 (AG N?rnberg) -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: OpenPGP digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160807/a5e61f3d/attachment.sig> ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support 2016-08-07 16:46 ` Andreas Färber @ 2016-08-07 20:07 ` Tom Rini 2016-08-08 21:44 ` Simon Glass 0 siblings, 1 reply; 17+ messages in thread From: Tom Rini @ 2016-08-07 20:07 UTC (permalink / raw) To: u-boot On Sun, Aug 07, 2016 at 06:46:37PM +0200, Andreas F?rber wrote: > Am 07.08.2016 um 15:31 schrieb Tom Rini: > > On Sat, Aug 06, 2016 at 06:05:29PM +0200, Andreas F?rber wrote: > >> Hi Simon, > >> > >> Am 06.08.2016 um 06:30 schrieb Simon Glass: > >>> Hi Andreas, > >>> > >>> On 17 July 2016 at 19:06, Andreas F?rber <afaerber@suse.de> wrote: > >>>> Hi, > >>>> > >>>> This series adds initial support for RK3368 SoC and GeekBox. > >>>> For more details see the commit message. > >>>> > >>>> Will need to be rebased onto Heiko's cleanups and Kever's RK3399 series. > >>>> > >>>> Regards, > >>>> Andreas > >>>> > >>>> Cc: Simon Glass <sjg@chromium.org> > >>>> Cc: Kever Yang <kever.yang@rock-chips.com> > >>>> Cc: Heiko St?bner <heiko@sntech.de> > >>>> > >>>> Andreas F?rber (2): > >>>> dts: Import rk3368-geekbox.dts > >>>> ARM64: rockchip: Add initial support for RK3368 based GeekBox > >>>> > >>> > >>> Are you planning to respin these patches? > >> > >> Eventually...? > >> > >>> I'd like to get them applied soon. > >> > >> And I'd like to get my work recognized! However, despite our previous > >> IRC chat, I had to find out _while_ replying to the rk3399 mails that > >> you had once again not just applied all patches (twenty minutes after > >> ack'ing them on a Saturday) but already sent a pull on Tuesday my > >> nighttime that I was not CC'ed on and that Tom has merged the night > >> after. So it feels like I'm wasting my time here and consequently I > >> stopped my review and rebase. > > > > In the U-Boot community, we are not in the habit of cc'ing everyone with > > a change in a given pull request. Is there a tool the kernel folks use > > here that makes this easy? > > Not that I'm aware of. > > But that is besides the point, as my very complaint is that I'm not > credited in the patches that got merged, so no tool could've extracted > my name for CC'ing. Alright. > It's about Simon having mismerged those patches and having overlooked > unresolved review comments of mine for those patches before and me > specifically having complained to him about not waiting for my > Reviewed-by before applying them. So him seeing that I did not reply to > his Saturday mails, I feel it would've been fair in this particular case > a) to ping me again after the weekend and b) to let me know that he is > no longer waiting for my review comments or that I really need to hurry > up with an objection until X. He did not say so in a reply that reached > my inbox, and I was not CC'ed on the pull request itself, thus a pull > request behind my back. > > I'm not too deep into U-Boot, so maybe there was a reason for this > hush-hush workflow, but then at least the communication was fairly bad. > > Had I known that the pull is already on the list, I wouldn't have > replied with a Reviewed-by for 1/4 that same day (which surely Simon was > CC'ed on) or I could've asked Tom to hold off merging it until I'm done > reviewing the next day. > > > And the rule of thumb that I use, and I try and get everyone else to use > > as well is that a patch should be out for a week before it gets picked > > up and merged as that should give everyone time to review, comment and > > test. Did that not happen with the patches Simon picked up? > > Slightly less than a week. For some other projects it's ~two weeks. > Also again note that this is not about some random patch but one where > Simon specifically said he would be away, that he would exchange the > patches on his branch where necessary and where he asked me to "sing". > It leaves a bad taste that Simon was absent himself the week the patches > were posted but apparently expects me to be available whenever he is. I > don't work on U-Boot as a job, and for rebasing rk3368 patches - which > many of my review comments resulted from - I need access to the hardware > for testing. > > Note that I was similarly surprised how quickly two patches of mine went > into his tree, with just one day in between and despite conflicts > between my rk3368 and Kever's rk3399 preparations. I can see that having > patches in a tree facilitates testing, but it also prevents serious peer > review when not just staging but also merging them. I want to treat all of the above at once. First, sorry. We don't have an intentionally "hush-hush" workflow, but every custodian does decide how many emails to send when moving a patch forward. And unless I'm testing multiple PRs (or they come in while I'm already testing one) the time between getting a PR and applying it is usually the same (US, east coast) day if it passes my testing. But we are trying to include more crediting, not less, so it is not intentional to have left things out[1]. So this was a mistake in our part, sorry. Sometimes review comments are missed. But this too is not usually intentional unless it's small things that can be addressed in a follow-up in order to get things otherwise in and unblocking other work. In the end however, Simon, please slow down a bit. It's OK if stuff misses a release, there's always the next one. And it may make sense to follow what Hans has been doing with the sunxi tree and having a next branch (which can always be rebased and stuff replaced in!) so it's both clear that patches are being picked up, but not rushing to get things in before a window closes. Thanks! -- Tom [1]: Patchwork had an outage recently and some stuff didn't make it in there and thus was missed unless picked up manually. Most tags come in via patchwork not manually adding to the commit message. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160807/454357e9/attachment.sig> ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support 2016-08-07 20:07 ` Tom Rini @ 2016-08-08 21:44 ` Simon Glass 0 siblings, 0 replies; 17+ messages in thread From: Simon Glass @ 2016-08-08 21:44 UTC (permalink / raw) To: u-boot Hi Tom, Andreas, On 7 August 2016 at 14:07, Tom Rini <trini@konsulko.com> wrote: > On Sun, Aug 07, 2016 at 06:46:37PM +0200, Andreas F?rber wrote: >> Am 07.08.2016 um 15:31 schrieb Tom Rini: >> > On Sat, Aug 06, 2016 at 06:05:29PM +0200, Andreas F?rber wrote: >> >> Hi Simon, >> >> >> >> Am 06.08.2016 um 06:30 schrieb Simon Glass: >> >>> Hi Andreas, >> >>> >> >>> On 17 July 2016 at 19:06, Andreas F?rber <afaerber@suse.de> wrote: >> >>>> Hi, >> >>>> >> >>>> This series adds initial support for RK3368 SoC and GeekBox. >> >>>> For more details see the commit message. >> >>>> >> >>>> Will need to be rebased onto Heiko's cleanups and Kever's RK3399 series. >> >>>> >> >>>> Regards, >> >>>> Andreas >> >>>> >> >>>> Cc: Simon Glass <sjg@chromium.org> >> >>>> Cc: Kever Yang <kever.yang@rock-chips.com> >> >>>> Cc: Heiko St?bner <heiko@sntech.de> >> >>>> >> >>>> Andreas F?rber (2): >> >>>> dts: Import rk3368-geekbox.dts >> >>>> ARM64: rockchip: Add initial support for RK3368 based GeekBox >> >>>> >> >>> >> >>> Are you planning to respin these patches? >> >> >> >> Eventually...? >> >> >> >>> I'd like to get them applied soon. >> >> >> >> And I'd like to get my work recognized! However, despite our previous >> >> IRC chat, I had to find out _while_ replying to the rk3399 mails that >> >> you had once again not just applied all patches (twenty minutes after >> >> ack'ing them on a Saturday) but already sent a pull on Tuesday my >> >> nighttime that I was not CC'ed on and that Tom has merged the night >> >> after. So it feels like I'm wasting my time here and consequently I >> >> stopped my review and rebase. >> > >> > In the U-Boot community, we are not in the habit of cc'ing everyone with >> > a change in a given pull request. Is there a tool the kernel folks use >> > here that makes this easy? >> >> Not that I'm aware of. >> >> But that is besides the point, as my very complaint is that I'm not >> credited in the patches that got merged, so no tool could've extracted >> my name for CC'ing. > > Alright. > >> It's about Simon having mismerged those patches and having overlooked >> unresolved review comments of mine for those patches before and me >> specifically having complained to him about not waiting for my >> Reviewed-by before applying them. So him seeing that I did not reply to >> his Saturday mails, I feel it would've been fair in this particular case >> a) to ping me again after the weekend and b) to let me know that he is >> no longer waiting for my review comments or that I really need to hurry >> up with an objection until X. He did not say so in a reply that reached >> my inbox, and I was not CC'ed on the pull request itself, thus a pull >> request behind my back. >> >> I'm not too deep into U-Boot, so maybe there was a reason for this >> hush-hush workflow, but then at least the communication was fairly bad. >> >> Had I known that the pull is already on the list, I wouldn't have >> replied with a Reviewed-by for 1/4 that same day (which surely Simon was >> CC'ed on) or I could've asked Tom to hold off merging it until I'm done >> reviewing the next day. >> >> > And the rule of thumb that I use, and I try and get everyone else to use >> > as well is that a patch should be out for a week before it gets picked >> > up and merged as that should give everyone time to review, comment and >> > test. Did that not happen with the patches Simon picked up? >> >> Slightly less than a week. For some other projects it's ~two weeks. >> Also again note that this is not about some random patch but one where >> Simon specifically said he would be away, that he would exchange the >> patches on his branch where necessary and where he asked me to "sing". >> It leaves a bad taste that Simon was absent himself the week the patches >> were posted but apparently expects me to be available whenever he is. I >> don't work on U-Boot as a job, and for rebasing rk3368 patches - which >> many of my review comments resulted from - I need access to the hardware >> for testing. >> >> Note that I was similarly surprised how quickly two patches of mine went >> into his tree, with just one day in between and despite conflicts >> between my rk3368 and Kever's rk3399 preparations. I can see that having >> patches in a tree facilitates testing, but it also prevents serious peer >> review when not just staging but also merging them. > > I want to treat all of the above at once. First, sorry. We don't have > an intentionally "hush-hush" workflow, but every custodian does decide > how many emails to send when moving a patch forward. And unless I'm > testing multiple PRs (or they come in while I'm already testing one) the > time between getting a PR and applying it is usually the same (US, east > coast) day if it passes my testing. But we are trying to include more > crediting, not less, so it is not intentional to have left things > out[1]. So this was a mistake in our part, sorry. Sometimes review > comments are missed. But this too is not usually intentional unless > it's small things that can be addressed in a follow-up in order to get > things otherwise in and unblocking other work. In the end however, > Simon, please slow down a bit. It's OK if stuff misses a release, > there's always the next one. And it may make sense to follow what Hans > has been doing with the sunxi tree and having a next branch (which can > always be rebased and stuff replaced in!) so it's both clear that > patches are being picked up, but not rushing to get things in before a > window closes. Thanks! OK thanks Tom for looking at this. I'll slow down a bit on the Rockchip stuff. I'll look at using a -next branch for that also. Andreas let me know how things go. I'd really like to see a review for new patches within a week if possible (absent holidays, etc.). > > -- > Tom > > [1]: Patchwork had an outage recently and some stuff didn't make it in > there and thus was missed unless picked up manually. Most tags come in > via patchwork not manually adding to the commit message. Yes that was a pain! Regards, SImon ^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support 2016-07-18 1:06 [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support Andreas Färber ` (2 preceding siblings ...) 2016-08-06 4:30 ` [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support Simon Glass @ 2016-08-29 7:17 ` Peter Robinson 3 siblings, 0 replies; 17+ messages in thread From: Peter Robinson @ 2016-08-29 7:17 UTC (permalink / raw) To: u-boot Hi, > This series adds initial support for RK3368 SoC and GeekBox. > For more details see the commit message. > > Will need to be rebased onto Heiko's cleanups and Kever's RK3399 series. Did you ever get a chance to rebase these? Wouldn't mind playing with my geekbox with an upstream u-boot. Regards, Peter ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2016-08-29 7:17 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-07-18 1:06 [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support Andreas Färber 2016-07-18 1:06 ` [U-Boot] [PATCH 1/2] dts: Import rk3368-geekbox.dts Andreas Färber 2016-07-18 11:56 ` Simon Glass 2016-07-18 1:06 ` [U-Boot] [PATCH 2/2] ARM64: rockchip: Add initial support for RK3368 based GeekBox Andreas Färber 2016-07-18 1:22 ` Andreas Färber 2016-07-18 11:56 ` Simon Glass 2016-07-18 12:13 ` Heiko Stübner 2016-07-23 2:31 ` Simon Glass 2016-07-25 14:46 ` Andreas Färber 2016-08-06 4:30 ` [U-Boot] [PATCH 0/2] rockchip: Initial RK3368 and GeekBox support Simon Glass 2016-08-06 16:05 ` Andreas Färber 2016-08-06 18:52 ` Simon Glass 2016-08-07 13:31 ` Tom Rini 2016-08-07 16:46 ` Andreas Färber 2016-08-07 20:07 ` Tom Rini 2016-08-08 21:44 ` Simon Glass 2016-08-29 7:17 ` Peter Robinson
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