From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
Date: Tue, 13 Apr 2021 00:17:15 -0400 [thread overview]
Message-ID: <17842260-088a-7e20-bcae-3e0ee9fac9fc@gmail.com> (raw)
In-Reply-To: <CAN5B=eJCV3ByexhPKHes5gqyM_G+QQokDPA7NFYOOgJjz3qQgg@mail.gmail.com>
On 4/13/21 12:12 AM, Rick Chen wrote:
> Hi Sean
>
>> On 4/12/21 10:39 PM, Rick Chen wrote:
>>> Hi Green,
>>>
>>>> From: Green Wan [mailto:green.wan at sifive.com]
>>>> Sent: Monday, April 12, 2021 10:33 AM
>>>> To: Sean Anderson
>>>> Cc: Rick Chen; Rick Jian-Zhi Chen(???); Bin Meng; U-Boot Mailing List; Paul Walmsley; Pragnesh Patel; Simon Glass; Atish Patra; Leo Yu-Chi Liang(???); Brad Kim
>>>> Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
>>>>
>>>> Hi Bin and Sean,
>>>>
>>>> While we keep the consistency of cache control discussion going, later
>>>> today I'd like to send the v5 patch which is not directly relevant to
>>>> cache control.
>>>
>>> I will prefer not to mix cache control issue into this patch.
>>> Like I said, this callback is a init for all harts before lottery.
>>
>> Yes, but enabling caches is a very similar thing (this proposal even
>> uses it to turn on caches, among other things). At the moment we have
>> two calls to enable caches at almost the same time as what Green
>> proposes. These calls only translate into work done on one platform. I
>> think having one call (or perhaps two) for this purpose would help
>> reduce codepaths across different platforms going forward.
>>
>
> Maybe we can add two callbacks (early_lottery_init and
> late_lottery_init) before and after lottery individually for all
> scenarios.
Yes, that is a possibility. But do we actually need that flexibility?
This comes back around to my original question: why does ax25 disable
cache on all harts before jumping to Linux?
And of course, does this actually need to be done before the lottery?
--Sean
next prev parent reply other threads:[~2021-04-13 4:17 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-30 5:26 [RFC PATCH v4 0/2] arch: riscv: cpu: Add callback to init each core Green Wan
2021-03-30 5:26 ` [RFC PATCH v4 1/2] " Green Wan
2021-04-02 22:53 ` Sean Anderson
2021-04-06 9:15 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5E931A0@ATCPCS12.andestech.com>
2021-04-09 8:16 ` Rick Chen
2021-04-09 13:17 ` Sean Anderson
2021-04-09 16:05 ` Green Wan
2021-04-11 15:43 ` Sean Anderson
2021-04-12 2:33 ` Green Wan
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5E95C00@ATCPCS12.andestech.com>
2021-04-13 2:39 ` Rick Chen
2021-04-13 2:42 ` Green Wan
2021-04-13 2:54 ` Sean Anderson
2021-04-13 4:12 ` Rick Chen
2021-04-13 4:17 ` Sean Anderson [this message]
2021-04-13 8:47 ` Green Wan
2021-04-14 1:05 ` Rick Chen
2021-04-16 12:42 ` Sean Anderson
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5E95C2F@ATCPCS12.andestech.com>
2021-04-13 3:33 ` Rick Chen
2021-04-13 8:21 ` Green Wan
2021-03-30 5:26 ` [RFC PATCH v4 2/2] board: sifive: unmatched: clear feature disable CSR Green Wan
2021-04-06 9:16 ` Bin Meng
2021-04-06 15:35 ` Green Wan
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