From mboxrd@z Thu Jan  1 00:00:00 1970
From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= <benoit.thebaudeau@advansee.com>
Date: Sat, 30 Mar 2013 16:42:19 +0100 (CET)
Subject: [U-Boot] [PATCH v9 01/30] mtd: nand: Introduce
 CONFIG_SYS_NAND_BUSWIDTH_16BIT
In-Reply-To: <20130330095231.6239f20e@lilith>
References: <1362596377-5827-1-git-send-email-benoit.thebaudeau@advansee.com>
	<20130330095231.6239f20e@lilith>
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To: u-boot@lists.denx.de

Hi Albert,

On Saturday, March 30, 2013 9:52:31 AM, Albert ARIBAUD wrote:
> Hi Beno?t,
> 
> On Wed,  6 Mar 2013 19:59:07 +0100, Beno?t Th?baudeau
> <benoit.thebaudeau@advansee.com> wrote:
> 
> > From: Fabio Estevam <fabio.estevam@freescale.com>
> > 
> > Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND
> > controller
> > drivers could use it when a 16-bit NAND is deployed.
> > 
> > drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that
> > other NAND drivers could reuse the same symbol.
> > 
> > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> > Reviewed-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > ---
> > Changes in v9: None
> > Changes in v8:
> >  - New patch.
> > 
> > Changes in v7: None
> > Changes in v6: None
> > Changes in v5: None
> > Changes in v4: None
> > Changes in v3: None
> > Changes in v2: None
> > 
> >  README                  |    9 ++++++---
> >  drivers/mtd/nand/ndfc.c |    4 ++--
> >  2 files changed, 8 insertions(+), 5 deletions(-)
> > 
> > diff --git a/README b/README
> > index d8cb394..830c45e 100644
> > --- a/README
> > +++ b/README
> > @@ -3713,9 +3713,12 @@ Low Level (hardware related) configuration options:
> >  - CONFIG_SYS_SRIOn_MEM_SIZE:
> >  		Size of SRIO port 'n' memory region
> >  
> > -- CONFIG_SYS_NDFC_16
> > -		Defined to tell the NDFC that the NAND chip is using a
> > -		16 bit bus.
> > +- CONFIG_SYS_NAND_BUSWIDTH_16BIT
> > +		Defined to tell the NAND controller that the NAND chip is using
> > +		a 16 bit bus.
> > +		Not all NAND drivers use this symbol.
> > +		Example of driver that uses it:
> > +		- drivers/mtd/nand/ndfc.c
> >  
> >  - CONFIG_SYS_NDFC_EBC0_CFG
> >  		Sets the EBC0_CFG register for the NDFC. If not defined
> > diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
> > index 6ebbb5e..213d2c9 100644
> > --- a/drivers/mtd/nand/ndfc.c
> > +++ b/drivers/mtd/nand/ndfc.c
> > @@ -156,7 +156,7 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd)
> >  
> >  	struct nand_chip *chip = mtd->priv;
> >  
> > -#ifdef CONFIG_SYS_NDFC_16BIT
> > +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
> >  	return (uint8_t) readw(chip->IO_ADDR_R);
> >  #else
> >  	return readb(chip->IO_ADDR_R);
> > @@ -218,7 +218,7 @@ int board_nand_init(struct nand_chip *nand)
> >  	nand->ecc.bytes = 3;
> >  	nand->select_chip = ndfc_select_chip;
> >  
> > -#ifdef CONFIG_SYS_NDFC_16BIT
> > +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
> >  	nand->options |= NAND_BUSWIDTH_16;
> >  #endif
> >  
> 
> Series does not apply cleanly on current mainline/ARM trees (actually,
> it does not rebase cleanly). I am trying fixing this manually for
> testings, but a rebased V10 will be necessary anyway.

OK, I'll send that on Monday, April 8, in the evening.

Best regards,
Beno?t