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[82.149.19.102]) by smtp.gmail.com with ESMTPSA id pg8-20020a170907204800b0078c1e174e11sm1822512ejb.136.2022.10.12.14.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Oct 2022 14:42:29 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Jagan Teki , Andre Przywara Cc: Icenowy Zheng , Jesse Taube , Yifan Gu , Giulio Benetti , George Hilliard , Samuel Holland , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: Re: [PATCH 4/6] sunxi: f1c100: add UART1 support Date: Wed, 12 Oct 2022 23:42:28 +0200 Message-ID: <1917971.yKVeVyVuyW@kista> In-Reply-To: <20221012163458.1968900-5-andre.przywara@arm.com> References: <20221012163458.1968900-1-andre.przywara@arm.com> <20221012163458.1968900-5-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Andre, Dne sreda, 12. oktober 2022 ob 18:34:56 CEST je Andre Przywara napisal(a): > Some boards use UART1 for its debug UART, so define the pins for the SPL > and the pinmux name and mux value for U-Boot proper. > > Signed-off-by: Andre Przywara > --- > arch/arm/mach-sunxi/board.c | 4 ++++ > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + > 2 files changed, 5 insertions(+) > > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c > index 62bb40b8c89..77216157908 100644 > --- a/arch/arm/mach-sunxi/board.c > +++ b/arch/arm/mach-sunxi/board.c > @@ -147,6 +147,10 @@ static int gpio_init(void) > sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); > sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); > sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); > +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) > + sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); > + sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); > + sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); > #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) > sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); > sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 9ce2bc1b3af..061104be056 > 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > @@ -245,6 +245,7 @@ static const struct sunxi_pinctrl_function > suniv_f1c100s_pinctrl_functions[] = { #else > { "uart0", 5 }, /* PE0-PE1 */ > #endif > + { "uart1", 5 }, /* PA0-PA3 */ Comment should be PA2-PA3. With that fixed: Reviewed-by: Jernej Skrabec Best regards, Jernej > }; > > static const struct sunxi_pinctrl_desc __maybe_unused > suniv_f1c100s_pinctrl_desc = { -- > 2.25.1