[U-Boot-Users] U-Boot and MPC857T?

[U-Boot-Users] U-Boot and MPC857T?

[Steven Scholz]

Hi there,

has someone patched U-Boot to "support" the MPC857T?

AFAIK it's basicly a MPC855T. So the only change would be to avoid a 
boot message like:

CPU:   unknown MPC855 (0x07000003) at 80 MHz: 4 kB I-Cache 4 kB 
D-Cache FEC present

*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***

Thanks,

Steven

[U-Boot-Users] U-Boot and MPC857T?

[Wolfgang Denk]

In message <3F014BE5.3080906@imc-berlin.de> you wrote:
> 
> has someone patched U-Boot to "support" the MPC857T?
> 
> AFAIK it's basicly a MPC855T. So the only change would be to avoid a 
> boot message like:
> 
> CPU:   unknown MPC855 (0x07000003) at 80 MHz: 4 kB I-Cache 4 kB 
> D-Cache FEC present

All  you  need  to  do  is  extend  the  list  of  types  defined  in
"cpu/mpc8xx/cpu.c" - a patch is welcome.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
Just go with the flow control, roll with the crunches, and, when  you
get a prompt, type like hell.

[U-Boot-Users] U-Boot and MPC857T?

[Steven Scholz]

Wolfgang Denk wrote:
> In message <3F014BE5.3080906@imc-berlin.de> you wrote:
> 
>>has someone patched U-Boot to "support" the MPC857T?
>>
>>AFAIK it's basicly a MPC855T. So the only change would be to avoid a 
>>boot message like:
>>
>>CPU:   unknown MPC855 (0x07000003) at 80 MHz: 4 kB I-Cache 4 kB 
>>D-Cache FEC present
> 
> 
> All  you  need  to  do  is  extend  the  list  of  types  defined  in
> "cpu/mpc8xx/cpu.c" - a patch is welcome.

I'd love to present a patch.
Could you please give me a pointer where to find information about the 
values of

k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);

?
I couldn't find some.

Is it possible to find out if it's a 855, 857 or 860 at runtime?
So that we don't have to rely on DEFINES?

FAIK MPC855T and MPC857T are basicly the same. So could put both on my 
board without actually changing the firmware.
Would be nice if u-boot could figure out which one is actually present.


Thanks,

Steven

[U-Boot-Users] U-Boot and MPC857T?

[Gunnar Larisch]

Hello!

On Wed, Jul 02, 2003 at 08:36:24AM +0200, Steven Scholz wrote:
> Wolfgang Denk wrote:
> >In message <3F014BE5.3080906@imc-berlin.de> you wrote:
> >
> >>has someone patched U-Boot to "support" the MPC857T?

Sorry, I am still using PPCBoot V1.6 and made a quick hack for some performance
tests.

> >>
> >>AFAIK it's basicly a MPC855T. So the only change would be to avoid a 
> >>boot message like:
> >>
> >>CPU:   unknown MPC855 (0x07000003) at 80 MHz: 4 kB I-Cache 4 kB 
> >>D-Cache FEC present
> >
> >
> >All  you  need  to  do  is  extend  the  list  of  types  defined  in
> >"cpu/mpc8xx/cpu.c" - a patch is welcome.
> 
> I'd love to present a patch.

Hope, this helps for a good patch.

> Could you please give me a pointer where to find information about the 
> values of
> 
> k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
> 
> ?
> I couldn't find some.

I couldn't neither. I patched the orginal check_CPU function for MPC855
and inserted a call like this:
+  case 0x07000003:
+       return (check_CPU_MPC857_HACK(clock, pvr, immr));
+       break;

so function check_CPU_MPC857_HACK is almost a copy of check_CPU.
the main differences in compare to check_CPU was this:
+  char  pre = 'X';
+  char *mid = "xx";
+  char *suf;
...
+  switch(k) {
+  case 0x07000003: mid = "T"; suf = "B"; m = 1; break;
+  default:                     suf = NULL;     break;
+  }
...
+  if (suf)
+       printf ("%cPC857%sZPnn%s", pre, mid, suf);
+  else
+       printf ("unknown MPC857 (0x%08x)", k);
+
+  printf(" at %s MHz:", strmhz(buf, clock));

> Is it possible to find out if it's a 855, 857 or 860 at runtime?

This would be really nice, that is the reason why I first tried the hack like
above, but we would have to modify some part of the macro concept.

> So that we don't have to rely on DEFINES?
> 
> FAIK MPC855T and MPC857T are basicly the same. So could put both on my 
> board without actually changing the firmware.
> Would be nice if u-boot could figure out which one is actually present.

I also thought to that, but it is not so easy, because of at least the
following Macros showed below.

We have our board with a MPC855T 50 MHz and two prototypes with a MPC857T 100
MHz. The CPU-Clock cannot be detected automatically. We need at
least the following differences:

#elif defined(CONFIG_100MHz)   /* for 100 MHz  = "50 MHz" |= SCCR_EBDF01 */
#define CFG_SCCR       (SCCR_TBS     | SCCR_EBDF01 | \
                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
                        SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
                        SCCR_RTSEL   | SCCR_DFALCD00)
#define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
#define CONFIG_8xx_GCLK_FREQ    100000000
#else                  /* up to 50 MHz we use a 1:1 clock (CLKOUT=GCLK2) */
#define CFG_SCCR       (SCCR_TBS     | \
                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
                        SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
                        SCCR_RTSEL   | SCCR_DFALCD00)
#define CFG_PLPRCR ( (2-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
#define CONFIG_8xx_GCLK_FREQ     50000000
#endif /* CONFIG_...MHz */

also CFG_MAMR_PTA should be modified.

Best regards,

Gunnar Larisch
-- 
Gunnar Larisch
Dipl.-Ing.
Development
Softing AG
Richard-Reitzner-Allee 6
85540 Haar

[U-Boot-Users] U-Boot and MPC857T?

[nyet at mrv.com]

motorola has sever pvr/immr/dparam references on the site.

the only chips you can't distinguish from each other are the new 866
family.

i also have a large 8xx patch i am working on to support that and the
new ADS board.

On Wed, Jul 02, 2003 at 08:36:24AM +0200, Steven Scholz wrote:
> Wolfgang Denk wrote:
> >In message <3F014BE5.3080906@imc-berlin.de> you wrote:
> >
> >>has someone patched U-Boot to "support" the MPC857T?
> >>
> >>AFAIK it's basicly a MPC855T. So the only change would be to avoid a 
> >>boot message like:
> >>
> >>CPU:   unknown MPC855 (0x07000003) at 80 MHz: 4 kB I-Cache 4 kB 
> >>D-Cache FEC present
> >
> >
> >All  you  need  to  do  is  extend  the  list  of  types  defined  in
> >"cpu/mpc8xx/cpu.c" - a patch is welcome.
> 
> I'd love to present a patch.
> Could you please give me a pointer where to find information about the 
> values of
> 
> k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
> 
> ?
> I couldn't find some.
> 
> Is it possible to find out if it's a 855, 857 or 860 at runtime?
> So that we don't have to rely on DEFINES?
> 
> FAIK MPC855T and MPC857T are basicly the same. So could put both on my 
> board without actually changing the firmware.
> Would be nice if u-boot could figure out which one is actually present.
> 
> 
> Thanks,
> 
> Steven
> 
> 
> 
> 
> 
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[U-Boot-Users] U-Boot and MPC857T?

[Steven Scholz]

Hi Gunnar,

> ...
> I also thought to that, but it is not so easy, because of at least the
> following Macros showed below.
> 
> We have our board with a MPC855T 50 MHz and two prototypes with a MPC857T 100
> MHz. The CPU-Clock cannot be detected automatically. We need at
> least the following differences:
> 
> #elif defined(CONFIG_100MHz)   /* for 100 MHz  = "50 MHz" |= SCCR_EBDF01 */
> #define CFG_SCCR       (SCCR_TBS     | SCCR_EBDF01 | \
>                         SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
>                         SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
>                         SCCR_RTSEL   | SCCR_DFALCD00)
> #define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
> #define CONFIG_8xx_GCLK_FREQ    100000000
> #else                  /* up to 50 MHz we use a 1:1 clock (CLKOUT=GCLK2) */
> #define CFG_SCCR       (SCCR_TBS     | \
>                         SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
>                         SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
>                         SCCR_RTSEL   | SCCR_DFALCD00)
> #define CFG_PLPRCR ( (2-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
> #define CONFIG_8xx_GCLK_FREQ     50000000
> #endif /* CONFIG_...MHz */

Ehm... I don't understand. The code above only depends on 
CONFIG_100MHz and not some CONFIG_MPC855T!
Of course you have to compile for a specific clock frequency. But it 
shouldn't matter if it's a 855T or a 857T!

That's why I thought the FW (compiled for one specific clock) should 
be able to detect the processor typ...

Steven

[U-Boot-Users] U-Boot and MPC857T?

[Steven Scholz]

nyet at mrv.com schrieb:
> motorola has sever pvr/immr/dparam references on the site.

Any chance you can provide a URL?


> i also have a large 8xx patch i am working on to support that and the
> new ADS board.

Do you mind to show us some lines in advance?

Steven

[U-Boot-Users] U-Boot and MPC857T?

[Gunnar Larisch]

On Wed, Jul 02, 2003 at 01:36:07PM +0200, Steven Scholz wrote:
> Hi Gunnar,
> 
> >...
> >I also thought to that, but it is not so easy, because of at least the
> >following Macros showed below.
> >
> >We have our board with a MPC855T 50 MHz and two prototypes with a MPC857T 
> >100
> >MHz. The CPU-Clock cannot be detected automatically. We need at
> >least the following differences:
> >
> >#elif defined(CONFIG_100MHz)   /* for 100 MHz  = "50 MHz" |= SCCR_EBDF01 */
> >#define CFG_SCCR       (SCCR_TBS     | SCCR_EBDF01 | \
> >                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
> >                        SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
> >                        SCCR_RTSEL   | SCCR_DFALCD00)
> >#define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
> >#define CONFIG_8xx_GCLK_FREQ    100000000
> >#else                  /* up to 50 MHz we use a 1:1 clock (CLKOUT=GCLK2) */
> >#define CFG_SCCR       (SCCR_TBS     | \
> >                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
> >                        SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
> >                        SCCR_RTSEL   | SCCR_DFALCD00)
> >#define CFG_PLPRCR ( (2-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
> >#define CONFIG_8xx_GCLK_FREQ     50000000
> >#endif /* CONFIG_...MHz */
> 
> Ehm... I don't understand. The code above only depends on 
> CONFIG_100MHz and not some CONFIG_MPC855T!

Yes, I would like to have more, like this:
  Identify processor and set Clock for that processor right.

> Of course you have to compile for a specific clock frequency. But it 

I hoped not.

> shouldn't matter if it's a 855T or a 857T!

We only used a 857T instead of 855T because the 857T works with 100 MHz
internal (both with 50 MHz extern). 855T are only avaible up to 80 MHz.
Do you use another feature of the 857T?

> That's why I thought the FW (compiled for one specific clock) should 
> be able to detect the processor typ...

You are right, that is working except with the warning and our 857T
behaves the same (as slow) like a 855T.

Best regards,
Gunnar Larisch
-- 
Gunnar Larisch
Dipl.-Ing.
Development
Softing AG
Richard-Reitzner-Allee 6
85540 Haar

[U-Boot-Users] U-Boot and MPC857T?

[Nye Liu]

On Wed, Jul 02, 2003 at 01:37:59PM +0200, Steven Scholz wrote:
> nyet at mrv.com schrieb:
> >motorola has sever pvr/immr/dparam references on the site.
> 
> Any chance you can provide a URL?

I can't find it offhand, i got most of our docs via the FAE.

I'm off for the long weekend, i'll try to have URLS for you
when i get back.

> >i also have a large 8xx patch i am working on to support that and the
> >new ADS board.
> 
> Do you mind to show us some lines in advance?

The patch is still a huge mess, i dont think you want to see it yet ;)

I'll try to cc you my next submission to wolfgang, but im pretty
sure he wont accept it, so you may be stuck on a fork if you depend on
it; it just touches too much existing code right now.

-- 
Nye Liu
nliu at mrv.com
(818) 772-6235x248

"Who would be stupid enough to quote a fictitious character?"
	-- Don Quixote