[U-Boot-Users] PPC4xx: SDRAM detection (bug?)

[Roger Larsson <roger.larsson@norran.net>]

On Thursday 25 November 2004 19.42, llandre wrote:
> I have a question about SDRAM detection code (cpu/ppc4xx/sdram.c).
> I tested it with the following configurations:
> Configuration #1: 32 MB (2 chips), SDRAM clk = 133 MHz
> Configuration #2: 32 MB (2 chips), SDRAM clk = 111 MHz
> and everything worked fine.
>
> Then I tried the following:
> Configuration #3: 64 MB (2 chips), SDRAM clk = 111 MHz
> and the SDRAM does not work. U-Boot executes fine until it jumps to SDRAM
> after relocation.
> In this case, two chips K4S561632E-TI75 have been used.
> In my understanding the default value (0x07f00000) for the RTR register
> is wrong because these chips have a 64 ms/8k cycle refresh.
> Thus this register should be 0x03780000. I tried to change it
> but SDRAM did not work anyway. I suspect it is necessary to fix
> the TR register too or that the value for RTR is wrong.
> Any suggestions/remarks?

We are using the automatic SDRAM settings code
(cpu/ppc4xx/sdp_sdram.c, unsure about exact name sdp_...
Anyway I think you can use it for necessary calculations)

Have you configuread all four banks?

/RogerL