From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Sat, 5 Mar 2005 08:55:10 +0100 Subject: [U-Boot-Users] Using DCACHE instead of internal SRAM as the initial stack on PPC440GP? In-Reply-To: References: Message-ID: <200503050855.10608.sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Shawn, On Saturday 05 March 2005 03:07, Shawn Jin wrote: > I'm experimenting to set up the initial stack in DCACHE instead of > internal SRAM on Ebony. Our SoC only has a ppc440 core and no internal > SRAM available. > > I made more changes than what I reported yesterday > (http://sourceforge.net/mailarchive/message.php?msg_id=11062649). My > understanding on the initial stack is: > 1. CFG_INIT_RAM_ADDR is set to an address which nobody uses it. No > backup RAM is required. > 2. Config only this area cacheable. All others are caching inhibited. > > So I made the following changes on Ebony's uboot code. > 1. set CFG_INIT_RAM_ADDR to 0x40000000, no memory or peripherals use > this address space, and CFG_INIT_DCACHE_CS to 4. > 2. This address space is mapped to 0x1_4F00_0000, one of spared > peripheral areas. My TLB is set as follows. > > (gdb) mon tlb 0 8 > 0 : 00 f0000000 256MB V0 -> 1_f0000000 U:0000 -I-G- XWRXWR > 1 : 00 e0000000 256MB V0 -> 1_40000000 U:0000 -I-G- -WR-WR > 2 : 00 40000000 4KB V0 -> 1_4f000000 U:0000 ----- XWRXWR Tlb 1 and 2 seem to overlap in the physical addresses! > 3 : 00 00000000 256MB V0 -> 0_00000000 U:0000 -I-G- XWRXWR > 4 : 00 d0000000 256MB V0 -> 2_00000000 U:0000 -I-G- -WR-WR > 5 : 00 80000000 256MB V0 -> 3_00000000 U:0000 -I-G- -WR-WR > 6 : 00 00000000 1KB -0 -> 0_00000000 U:0000 ----- ------ > 7 : 00 00000000 1KB -0 -> 0_00000000 U:0000 ----- ------ > 8 : 00 00000000 1KB -0 -> 0_00000000 U:0000 ----- ------ > > 3. Commented out internal SRAM initialization and TLB entries. > 4. set up EBC bank 4 for this area. > /*----------------------------------------------------------------------- > */ /* Memory Bank x (nothingness) initialization */ > /* used as temporary stack pointer for stage0 */ > /*----------------------------------------------------------------------- > */ li r4, xbcfg > mtdcr ebccfga, r4 > lis r1, 0x0400 > ori r1, r1, 0x0000 > mfdcr r4, ebccfgd > or r4, r4, r1 > mtdcr ebccfgd, r4 /* set ATC */ > > li r4, PBxAP > mtdcr ebccfga, r4 > lis r4, 0x0380 > ori r4, r4, 0x0480 > mtdcr ebccfgd, r4 > > addi r4, 0, PBxCR > mtdcr ebccfga, r4 > lis r4, 0x4F01 /* BAS=0x4F0, BS=000 (1MB) */ > ori r4, r4, 0xE000 /* BU=11 (r/w), BW=11 (32 bits) */ You don't set BW to 11 but to 10. Please use 0x4f01f000 for the PBxCR value. I don't think this is the cause for the problem, but it can't hurt to correct this. > mtdcr ebccfgd, r4 > > However initializing the stack still causes machine check exception. I > really don't know what else I'm missing here. Any suggestions or hints > are greatly appreciated! Did you take a look at the error reporting registers (for example EBC0_BEAR / EBC0_BESR)? Best regards, Stefan