[U-Boot-Users] NAND flash support

[U-Boot-Users] NAND flash support

[Terence Soh]

Hi,

Correct me if I'm wrong but u-boot only support 512 byte page size nand 
flash components. Is there going to be any nand flash driver support for 
2048 bytes (8-bit data bus) page size components?

Thanks,
Terence.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.denx.de/pipermail/u-boot/attachments/20051031/7ffd584e/attachment.htm 

[U-Boot-Users] NAND flash support

[Wolfgang Denk]

In message <OFCE5A7B44.FA9F0802-ON482570AB.00300B9C-482570AB.003050F6@applera.com> you wrote:
>
> Correct me if I'm wrong but u-boot only support 512 byte page size nand 
> flash components. Is there going to be any nand flash driver support for 
> 2048 bytes (8-bit data bus) page size components?

The #testing-NAND branch ofthe U-Boot GIT repository contains a major
rewrite of NAND support. Unfortunately we  don't  make  any  progress
with  merging  it  into  the  main  branch because nobody seems to be
testing or using it.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There has been an alarming increase in the number of things you  know
nothing about.

[U-Boot-Users] NAND flash support

[Mike Rapoport]

On 10/31/05, Wolfgang Denk <wd@denx.de> wrote:
> The #testing-NAND branch ofthe U-Boot GIT repository contains a major
> rewrite of NAND support. Unfortunately we  don't  make  any  progress
> with  merging  it  into  the  main  branch because nobody seems to be
> testing or using it.
>

I've been trying to use the new NAND code on custom board based on
MPC8272 with Samsung 128Mb NAND chip (K9K1G08U0M). So far I had no
problems with read/dump functionality.
I've implemented the nand_erase wrapper in the include/nand.h and
after restoring the most of nand_wait in drivers/nand/nand_base.c the
erase worked for me.
The only thing that I haven't succeeded to enable is the write. When I
try to write relatively large chunks of data, there is a bus fault
just after I see the message
"NAND write: device 0 offset 0, size 1048576 ... 1048576 bytes written: OK".
Besides, the blocks that were written are marked bad.

The relevant parts of my board configuration are:
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE	0xff000000
#define CONFIG_NEW_NAND_CODE	1
#define CONFIG_MTD_DEBUG 1
#define CONFIG_MTD_DEBUG_VERBOSE	1

The functions for HW access are the same as I use in Linux mtd driver
which works fine.

--
	Sincerely Yours,
		Mike.

[U-Boot-Users] NAND flash support

[Ladislav Michl]

On Tue, Nov 01, 2005 at 09:46:33AM +0200, Mike Rapoport wrote:
> On 10/31/05, Wolfgang Denk <wd@denx.de> wrote:
> > The #testing-NAND branch ofthe U-Boot GIT repository contains a major
> > rewrite of NAND support. Unfortunately we  don't  make  any  progress
> > with  merging  it  into  the  main  branch because nobody seems to be
> > testing or using it.
> >
> 
> I've been trying to use the new NAND code on custom board based on
> MPC8272 with Samsung 128Mb NAND chip (K9K1G08U0M). So far I had no
> problems with read/dump functionality.
> I've implemented the nand_erase wrapper in the include/nand.h and
> after restoring the most of nand_wait in drivers/nand/nand_base.c the
> erase worked for me.

Could you please provide a patch?

> The only thing that I haven't succeeded to enable is the write. When I
> try to write relatively large chunks of data, there is a bus fault
> just after I see the message
> "NAND write: device 0 offset 0, size 1048576 ... 1048576 bytes written: OK".
> Besides, the blocks that were written are marked bad.
> 
> The relevant parts of my board configuration are:
> #define CFG_MAX_NAND_DEVICE 1
> #define CFG_NAND_BASE	0xff000000
> #define CONFIG_NEW_NAND_CODE	1
> #define CONFIG_MTD_DEBUG 1
> #define CONFIG_MTD_DEBUG_VERBOSE	1
> 
> The functions for HW access are the same as I use in Linux mtd driver
> which works fine.

What version of MTD code are you using in your Linux kernel? I'm just
updating U-Boot code to be based on what's contained in 2.6.14, which
_may_ address some problems people were reporting before. I hope to get
time to send update next week.

Thanks,
	ladis

[U-Boot-Users] NAND flash support

[Mike Rapoport]

On 11/1/05, Ladislav Michl <ladis@linux-mips.org> wrote:
> Could you please provide a patch?

I've tried to make it as clean as possible, but there still may be
some junk I used for debugging.

>
> What version of MTD code are you using in your Linux kernel? I'm just
> updating U-Boot code to be based on what's contained in 2.6.14, which
> _may_ address some problems people were reporting before. I hope to get
> time to send update next week.

I use kernel 2.6.12.3 and except a wrong ID for 512Mb NAND flashe, the
MTD code contained there works fine for me.


--
	Sincerely Yours,
		Mike.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: testing_NAND.erase.patch
Type: application/octet-stream
Size: 3895 bytes
Desc: not available
Url : http://lists.denx.de/pipermail/u-boot/attachments/20051101/9e77ff6c/attachment.obj 

[U-Boot-Users] NAND flash support

[Ladislav Michl]

On Tue, Nov 01, 2005 at 04:22:28PM +0200, Mike Rapoport wrote:
> I've tried to make it as clean as possible, but there still may be
> some junk I used for debugging.

Thanks a lot. Updated version (with timeout handling) follows - generated
against testing-NAND branch. Wolfgang, could you apply?

I also got another board with NAND chip for testing and I was able to
reproduce your problem with with bus error. I'll look at it as soon as
I get some spare time.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

CHANGELOG:
* Add hook to NAND erase and implement nand_wait function.
  Patch by Mike Rapoport, 1 Nov 2005
  
diff --git a/common/Makefile b/common/Makefile
--- a/common/Makefile
+++ b/common/Makefile
@@ -37,7 +37,7 @@ COBJS	= main.o ACEX1K.o altera.o bedbug.
 	  cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \
 	  cmd_load.o cmd_log.o \
 	  cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
-	  cmd_nand.o cmd_net.o cmd_nvedit.o \
+	  cmd_nand.o cmd_nand_new.o cmd_net.o cmd_nvedit.o \
 	  cmd_pci.o cmd_pcmcia.o cmd_portio.o \
 	  cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o cmd_usb.o cmd_vfd.o \
 	  command.o console.o devices.o dlmalloc.o docecc.o \
diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c
--- a/drivers/nand/nand_base.c
+++ b/drivers/nand/nand_base.c
@@ -189,7 +189,11 @@ static void nand_release_device (struct 
 	spin_unlock (&this->chip_lock);
 }
 #else
-#define nand_release_device(mtd)	do {} while(0)
+static void nand_release_device (struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	this->select_chip(mtd, -1);	/* De-select the NAND device */
+}
 #endif
 
 /**
@@ -831,8 +835,34 @@ static int nand_wait(struct mtd_info *mt
 #else
 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
 {
-	/* TODO */
-	return 0;
+	unsigned long	timeo;
+
+	if (state == FL_ERASING)
+		timeo = CFG_HZ * 400;
+	else
+		timeo = CFG_HZ * 20;
+
+	if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
+		this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
+	else
+		this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+
+	reset_timer_masked();
+
+	while (1) {
+		if (get_timer_masked() > timeo)
+			return 0;
+
+		if (this->dev_ready) {
+			if (this->dev_ready(mtd))
+				break;
+		} else {
+			if (this->read_byte(mtd) & NAND_STATUS_READY)
+				break;
+		}
+	}
+
+	return this->read_byte(mtd);
 }
 #endif
 
diff --git a/include/bmp_logo.h b/include/bmp_logo.h
diff --git a/include/nand.h b/include/nand.h
--- a/include/nand.h
+++ b/include/nand.h
@@ -50,7 +50,14 @@ static inline int nand_block_isbad(nand_
 
 static inline int nand_erase(nand_info_t *info, ulong off, ulong size)
 {
-	return 0; /* FIXME */
+	struct erase_info instr;
+
+	instr.mtd = info;
+	instr.addr = off;
+	instr.len = size;
+	instr.callback = 0;
+
+	return info->erase(info, &instr);
 }
 
 #endif

[U-Boot-Users] NAND flash support

[mitsy]

Hi,

I've been trying to add NAND flash support to my u-boot but having
issues. I'd really appreciate if anyone could give me any
suggestions/comments on what I'm doing wrong.

The board I have is based on AMD au1550, and it has one NOR flash and
one NAND flash. NAND flash is configured in lowlevel_init.S correctly
(I believe so since it works from Linux kernel.) However, when I try
to send any command to NAND flash, it just hangs there. Here are the
command macros I have:

#define NAND_WAIT_READY(nand)   while (!(*(volatile u8
*)((ulong)MEM_STSTAT) & 0x01))
#define WRITE_NAND_COMMAND(d, adr) do { printf("weee!"); *(volatile u8
*)((ulong)adr+MEM_STNAND_CMD) = d; __asm__ volatile ("sync"); }
while(0)
#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8
*)((ulong)adr+MEM_STNAND_ADDR) = d; __asm__ volatile ("sync");}
while(0)
#define WRITE_NAND(d, adr)      do {*(volatile u8
*)((ulong)adr+MEM_STNAND_DATA) = d; __asm__ volatile ("sync");}
while(0)
#define READ_NAND(adr)          (*(volatile u8 *)((ulong)adr+MEM_STNAND_DATA))
#define NAND_DISABLE_CE(nand)   do { *(volatile u8 *)(MEM_STNDCTL) =
0; __asm__ volatile ("sync");} while(0)
#define NAND_ENABLE_CE(nand)    do { *(volatile u8 *)(MEM_STNDCTL) =
(1<<5); __asm__ volatile ("sync");} while(0)

These are empty since the processor handles them.

#define NAND_CTL_CLRALE
#define NAND_CTL_SETALE
#define NAND_CTL_CLRCLE
#define NAND_CTL_SETCLE

Thank you for your help in advance!

Mitsy