* [U-Boot-Users] [PATCH] Update board NetStar
@ 2005-11-03 12:07 Ladislav Michl
2006-07-22 19:07 ` Wolfgang Denk
0 siblings, 1 reply; 4+ messages in thread
From: Ladislav Michl @ 2005-11-03 12:07 UTC (permalink / raw)
To: u-boot
Just to sync my local tree with public one. Generated against
testing-NAND branch.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
CHANGELOG:
* Update board NetStar
Patch by Ladislav Michl, 3 Nov 2005
diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S
--- a/board/netstar/crcek.S
+++ b/board/netstar/crcek.S
@@ -13,6 +13,7 @@
* u32 - crc32
*/
+#include <config.h>
#include "crcek.h"
/**
@@ -39,7 +40,7 @@
.macro crcuj, offset, size
mov r0, #0
ldr r1, \offset
- ldr r2, [r1]
+ ldr r2, [r1], #4
cmp r2, r0 @ no data, no problem
beq 2f
tst r2, #3 @ unaligned size
@@ -47,7 +48,6 @@
ldr r3, \size
cmp r2, r3 @ bogus size
bhi 2f
- add r1, r1, #4
do_crc32
ldr r1, [r1]
2:
@@ -55,16 +55,71 @@
.endm
.macro wait, reg
- mov \reg, #0x1000
+ mov \reg, #0x100000
3:
subs \reg, \reg, #0x1
bne 3b
-
.endm
+
.text
.globl crcek
crcek:
- b crc2_bad
+ /* Enable I-cache */
+ mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
+ mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
+ mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
+ orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
+ mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
+ mov r1, #0x00
+ mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
+ nop
+ nop
+ nop
+ nop
+
+ /* Setup clocking mode */
+ ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
+ ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
+ bic r1, r1, #(7 << 11) @ clear clock select
+ orr r1, r1, #(2 << 11) @ set synchronous scalable
+ mov r2, #0
+loop:
+ cmp r2, #1 @ this loop will wait for@least 100 cycles
+ streqh r1, [r0, #0x18] @ before issuing next request from MPU
+ add r2, r2, #1 @ on the 1st run code is loaded into I-cache
+ cmp r2, #16 @ and second run will set clocking mode
+ bne loop
+ nop
+
+ /* Setup clock dividers */
+ ldr r1, CKCTL_VAL
+ orr r1, r1, #0x2000 @ enable DSP clock
+ strh r1, [r0] @ setup clock divisors
+
+ /* Setup DPLL to generate requested freq */
+ ldr r0, DPLL1_BASE @ base of DPLL1 register
+ mov r1, #0x0010 @ set PLL_ENABLE
+ orr r1, r1, #0x2000 @ set IOB to new locking
+ orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+ orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+ strh r1, [r0] @ write
+
+locking:
+ ldrh r1, [r0] @ get DPLL value
+ tst r1, #0x01
+ beq locking @ while LOCK not set
+
+ /* Enable clock */
+ ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
+ mov r1, #(1 << 10) @ disable idle mode do not check
+ @ nWAKEUP pin, other remain active
+ strh r1, [r0, #0x04]
+ ldr r1, EN_CLK_VAL
+ strh r1, [r0, #0x08]
+ mov r1, #0x003f @ FLASH.RP not enabled in idle and
+ strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
+
+
mov r6, #0
crcuj _LOADER1_OFFSET, _LOADER_SIZE
bne crc1_bad
@@ -76,9 +131,8 @@ crc1_bad:
crc2_bad:
ldr r3, _LOADER1_OFFSET
ldr r4, _LOADER2_OFFSET
- b boot_2nd
- tst r6, #3
- beq one_is_bad @ one of them (or both) has bad crc
+ teq r6, #3
+ bne one_is_bad @ one of them (or both) has bad crc
ldr r1, [r3, #4]
ldr r2, [r4, #4]
cmp r1, r2 @ boot 2nd loader if versions differ
@@ -90,6 +144,7 @@ one_is_bad:
tst r6, #2
bne boot_2nd
@ We are doomed, so let user know.
+hell:
ldr r0, GPIO_BASE @ configure GPIO pins
ldr r1, GPIO_DIRECTION
strh r1, [r0, #0x08]
@@ -171,6 +226,15 @@ CRC32_TABLE:
GPIO_BASE:
.word 0xfffce000
+MPU_CLKM_BASE:
+ .word 0xfffece00
+DPLL1_BASE:
+ .word 0xfffecf00
+
+CKCTL_VAL:
+ .word OMAP5910_ARM_CKCTL
+EN_CLK_VAL:
+ .word OMAP5910_ARM_EN_CLK
GPIO_DIRECTION:
.word 0x0000ffe7
diff --git a/board/netstar/crcek.h b/board/netstar/crcek.h
diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c
--- a/board/netstar/crcit.c
+++ b/board/netstar/crcit.c
@@ -77,7 +77,7 @@ int main(int argc, char **argv)
} else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) {
char *endptr, *nptr = argv[2];
unsigned ver = strtoul(nptr, &endptr, 0);
- if (nptr != '\0' && endptr == '\0')
+ if (*nptr != '\0' && *endptr == '\0')
return doit(argv[3], ver);
}
fprintf(stderr, "Usage: crcit [-v version] <image>\n");
diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c
--- a/board/netstar/eeprom.c
+++ b/board/netstar/eeprom.c
@@ -213,3 +213,4 @@ int eeprom(int argc, char *argv[])
return 0;
}
+
diff --git a/board/netstar/nand.c b/board/netstar/nand.c
--- a/board/netstar/nand.c
+++ b/board/netstar/nand.c
@@ -55,10 +55,11 @@ static int netstar_nand_ready(struct mtd
void board_nand_init(struct nand_chip *nand)
{
- nand->options = NAND_SAMSUNG_LP_OPTIONS;
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
nand->eccmode = NAND_ECC_SOFT;
- nand->hwcontrol = netstar_nand_hwcontrol;
+ nand->hwcontrol = netstar_nand_hwcontrol;
/* nand->dev_ready = netstar_nand_ready; */
nand->chip_delay = 18;
}
#endif
+
diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c
--- a/board/netstar/netstar.c
+++ b/board/netstar/netstar.c
@@ -27,7 +27,6 @@ int board_init(void)
DECLARE_GLOBAL_DATA_PTR;
/* arch number of NetStar board */
- /* TODO: use define from asm/mach-types.h */
gd->bd->bi_arch_number = 692;
/* adress of boot parameters */
@@ -53,16 +52,13 @@ int dram_init(void)
return 0;
}
-extern void partition_flash(void);
-
int misc_init_r(void)
{
return 0;
}
-extern void nand_init(void);
-
int board_late_init(void)
{
return 0;
}
+
diff --git a/board/netstar/setup.S b/board/netstar/setup.S
--- a/board/netstar/setup.S
+++ b/board/netstar/setup.S
@@ -58,10 +58,10 @@ VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0)
VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
#endif
-VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
+VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
VAL_EMIFF_MRS: .word 0x00000037
-/*
+/*
* GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
* GPIO07 - LAN91C111 reset
*/
@@ -106,7 +106,7 @@ MUX_CONFIG_OFFSETS:
.align 1
.byte 0x00 @ FUNC_MUX_CTRL_0
.byte 0x04 @ FUNC_MUX_CTRL_1
- .byte 0x08 @ FUNC_MUX_CTRL_2
+ .byte 0x08 @ FUNC_MUX_CTRL_2
.byte 0x10 @ FUNC_MUX_CTRL_3
.byte 0x14 @ FUNC_MUX_CTRL_4
.byte 0x18 @ FUNC_MUX_CTRL_5
@@ -145,25 +145,23 @@ platformsetup:
nop
/* Setup clocking mode */
- ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit
- ldrh r1, [r0, #0x18] @ get reset status
+ ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
+ ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
bic r1, r1, #(7 << 11) @ clear clock select
orr r1, r1, #(2 << 11) @ set synchronous scalable
- mov r2, #0 @ set wait counter to 100 clock cycles
-
-icache_loop:
- cmp r2, #0x01
- streqh r1, [r0, #0x18]
- add r2, r2, #0x01
- cmp r2, #0x10
- bne icache_loop
+ mov r2, #0
+loop:
+ cmp r2, #1 @ this loop will wait for@least 100 cycles
+ streqh r1, [r0, #0x18] @ before issuing next request from MPU
+ add r2, r2, #1 @ on the 1st run code is loaded into I-cache
+ cmp r2, #16 @ and second run will set clocking mode
+ bne loop
nop
- /* Setup clock divisors */
- ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
+ /* Setup clock dividers */
ldr r1, _OMAP5910_ARM_CKCTL
orr r1, r1, #0x2000 @ enable DSP clock
- strh r1, [r0, #0x00] @ setup clock divisors
+ strh r1, [r0] @ setup clock divisors
/* Setup DPLL to generate requested freq */
ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
@@ -182,18 +180,17 @@ locking:
ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
mov r1, #(1 << 10) @ disable idle mode do not check
@ nWAKEUP pin, other remain active
- strh r1, [r0, #0x04]
+ strh r1, [r0, #0x04]
ldr r1, _OMAP5910_ARM_EN_CLK
strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and
- @ max delayed ( 32 x CLKIN )
- strh r1, [r0, #0x0c]
+ strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
/* Configure 5910 pins functions to match our board. */
ldr r0, MUX_CONFIG_BASE
adr r1, MUX_CONFIG_VALUES
adr r2, MUX_CONFIG_OFFSETS
-next_mux_cfg:
+next_mux_cfg:
ldrb r3, [r2], #1
ldr r4, [r1], #4
cmp r3, #0xff
@@ -240,15 +237,15 @@ next_mux_cfg:
strh r1, [r0, #0x34]
/* Setup clock divisors */
- ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
+ ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
mov r1, #0x0010 @ set PLL_ENABLE
- orr r1, r1, #0x2000 @ set IOB to new locking
- strh r1, [r0] @ write
+ orr r1, r1, #0x2000 @ set IOB to new locking
+ strh r1, [r0] @ write
ulocking:
ldrh r1, [r0] @ get DPLL value
- tst r1, #1
+ tst r1, #1
beq ulocking @ while LOCK not set
/* EMIF init */
@@ -257,7 +254,7 @@ ulocking:
bic r1, r1, #0x0c @ pwr down disabled, flash WP
orr r1, r1, #0x01
str r1, [r0, #0x0c]
-
+
ldr r1, VAL_EMIFS_CS0_CONFIG
str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
ldr r1, VAL_EMIFS_CS1_CONFIG
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot-Users] [PATCH] Update board NetStar
2005-11-03 12:07 [U-Boot-Users] [PATCH] Update board NetStar Ladislav Michl
@ 2006-07-22 19:07 ` Wolfgang Denk
0 siblings, 0 replies; 4+ messages in thread
From: Wolfgang Denk @ 2006-07-22 19:07 UTC (permalink / raw)
To: u-boot
In message <20051103120737.GB3894@orphique> you wrote:
>
> * Update board NetStar
> Patch by Ladislav Michl, 3 Nov 2005
Applied, thanks.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
To be a winner, all you need to give is all you have.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot-Users] [PATCH] Update board NetStar
@ 2007-05-24 15:21 Ladislav Michl
2007-05-24 15:46 ` Peter Pearse
0 siblings, 1 reply; 4+ messages in thread
From: Ladislav Michl @ 2007-05-24 15:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
diff --git a/Makefile b/Makefile
index caa5a0e..9a34e14 100644
--- a/Makefile
+++ b/Makefile
@@ -1954,17 +1954,8 @@ mx1ads_config : unconfig
mx1fs2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx
-netstar_32_config \
netstar_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _32_,$@)" ] ; then \
- echo "... 32MB SDRAM" ; \
- echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>$(obj)include/config.h ; \
- else \
- echo "... 64MB SDRAM" ; \
- echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>$(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -a netstar arm arm925t netstar
+ @$(MKCONFIG) $(@:_config=) arm arm925t netstar
omap1510inn_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
diff --git a/board/netstar/nand.c b/board/netstar/nand.c
index 7852365..eea7455 100644
--- a/board/netstar/nand.c
+++ b/board/netstar/nand.c
@@ -45,23 +45,12 @@ static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd)
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
-/*
- * chip R/B detection
- */
-/***
-static int netstar_nand_ready(struct mtd_info *mtd)
-{
- return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02;
-}
-***/
-
int board_nand_init(struct nand_chip *nand)
{
nand->options = NAND_SAMSUNG_LP_OPTIONS;
nand->eccmode = NAND_ECC_SOFT;
nand->hwcontrol = netstar_nand_hwcontrol;
-/* nand->dev_ready = netstar_nand_ready; */
- nand->chip_delay = 18;
+ nand->chip_delay = 400;
return 0;
}
#endif
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 697796a..1a685df 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -48,14 +48,14 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-#define CFG_DEVICE_NULLDEV 1 /* enable null device */
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
-
+#define CFG_CONSOLE_INFO_QUIET
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
/*
@@ -63,30 +63,21 @@
*/
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_MAX_FLASH_BANKS 1
-#if (PHYS_SDRAM_1_SIZE == SZ_32M)
-/*#if 1*/
-#define CFG_FLASH_CFI /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_MAX_FLASH_SECT 128
-#else
-#define PHYS_FLASH_1_SIZE SZ_1M
+#define PHYS_FLASH_1_SIZE (1 * 1024 * 1024)
#define CFG_MAX_FLASH_SECT 19
#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */
#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ)
-#endif
#define CFG_MONITOR_BASE PHYS_FLASH_1
-#define CFG_MONITOR_LEN SZ_256K
+#define CFG_MONITOR_LEN (256 * 1024)
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH
-#define ENV_IS_SOLITARY
#define CFG_ENV_ADDR 0x4000
-#define CFG_ENV_SIZE SZ_8K
-#define CFG_ENV_SECT_SIZE SZ_8K
+#define CFG_ENV_SIZE (8 * 1024)
+#define CFG_ENV_SECT_SIZE (8 * 1024)
#define CFG_ENV_ADDR_REDUND 0x6000
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
#define CONFIG_ENV_OVERWRITE
@@ -95,14 +86,12 @@
* Size of malloc() pool
*/
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-/* XXX #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)*/
-#define CFG_MALLOC_LEN SZ_4M
+#define CFG_MALLOC_LEN (4 * 1024 * 1024)
/*
* The stack size is set up in start.S using the settings below
*/
-/* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */
-#define CONFIG_STACKSIZE SZ_1M /* regular stack */
+#define CONFIG_STACKSIZE (1 * 1024 * 1024) /* regular stack */
/*
* Hardware drivers
@@ -132,36 +121,25 @@
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE 0x04000000 + (2 << 23)
+#define NAND_ALLOW_ERASE_ALL 1
/*
- * JFFS2 partitions (mtdparts command line support)
+ * partitions (mtdparts command line support)
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0"
-#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k at 16k(env),8k(r_env),448k at 576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
+#define MTDPARTS_DEFAULT "mtdparts=" \
+ "omapflash.0:8k at 16k(env),8k(r_env),448k@576k(u-boot);" \
+ "omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
-#if 0
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_BOOTD | \
- CFG_CMD_DHCP | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_LOADB | \
- CFG_CMD_NET | \
- CFG_CMD_MEMORY | \
- CFG_CMD_PING | \
- CFG_CMD_RUN)
-
-#else
#define CONFIG_COMMANDS (CFG_CMD_BDI | \
CFG_CMD_BOOTD | \
CFG_CMD_DHCP | \
CFG_CMD_ENV | \
CFG_CMD_FLASH | \
+ CFG_CMD_JFFS2 | \
CFG_CMD_NAND | \
CFG_CMD_IMI | \
- CFG_CMD_JFFS2 | \
CFG_CMD_LOADB | \
CFG_CMD_NET | \
CFG_CMD_MEMORY | \
@@ -169,7 +147,6 @@
CFG_CMD_RUN)
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#endif
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
#define CONFIG_LOOPW
@@ -181,36 +158,31 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CFG_AUTOLOAD "n" /* No autoload */
-#define CONFIG_BOOTCOMMAND "run nboot"
+#define CONFIG_BOOTCOMMAND "run fboot"
#define CONFIG_PREBOOT "run setup"
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=yes\0" \
+ "ospart=0\0" \
"setup=setenv bootargs console=ttyS0,$baudrate " \
"$mtdparts\0" \
- "ospart=0\0" \
"setpart=" \
"if test -n $swapos; then " \
- "if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\
"setenv swapos; saveenv; " \
- "else " \
- "chpart nand0,$ospart; " \
+ "if test $ospart -eq 0; then setenv ospart 1; else setenv ospart 0; fi; "\
"fi\0" \
"nfsargs=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
"nfsroot=$rootpath root=/dev/nfs\0" \
"flashargs=run setpart;setenv bootargs $bootargs " \
- "root=/dev/mtdblock$partition ro " \
+ "root=mtd:rootfs$ospart ro " \
"rootfstype=jffs2\0" \
- "initrdargs=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
- "iboot=bootp;run initrdargs;tftp;bootm\0" \
- "fboot=run flashargs;fsload /boot/uImage;bootm\0" \
- "nboot=bootp;run nfsargs;tftp;bootm\0"
+ "fboot=run flashargs;nboot kernel$ospart\0" \
+ "nboot=bootp;run nfsargs;tftp\0"
#if 0 /* feel free to disable for development */
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
-#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n"
-#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */
-#define CONFIG_BOOT_RETRY_TIME 30
+#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d secs...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */
#endif
/*
@@ -228,7 +200,8 @@
#define CONFIG_AUTO_COMPLETE
#define CFG_MEMTEST_START PHYS_SDRAM_1
-#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
+#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
+ (CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE)
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot-Users] [PATCH] Update board NetStar
2007-05-24 15:21 Ladislav Michl
@ 2007-05-24 15:46 ` Peter Pearse
0 siblings, 0 replies; 4+ messages in thread
From: Peter Pearse @ 2007-05-24 15:46 UTC (permalink / raw)
To: u-boot
Received
> -----Original Message-----
> From: Ladislav Michl [mailto:ladis at linux-mips.org]
> Sent: 24 May 2007 16:22
> To: Peter Pearse
> Cc: uboot
> Subject: [PATCH] Update board NetStar
>
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
>
> diff --git a/Makefile b/Makefile
> index caa5a0e..9a34e14 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1954,17 +1954,8 @@ mx1ads_config : unconfig
> mx1fs2_config : unconfig
> @$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx
>
> -netstar_32_config \
> netstar_config: unconfig
> - @mkdir -p $(obj)include
> - @if [ "$(findstring _32_,$@)" ] ; then \
> - echo "... 32MB SDRAM" ; \
> - echo "#define PHYS_SDRAM_1_SIZE SZ_32M"
> >>$(obj)include/config.h ; \
> - else \
> - echo "... 64MB SDRAM" ; \
> - echo "#define PHYS_SDRAM_1_SIZE SZ_64M"
> >>$(obj)include/config.h ; \
> - fi
> - @$(MKCONFIG) -a netstar arm arm925t netstar
> + @$(MKCONFIG) $(@:_config=) arm arm925t netstar
>
> omap1510inn_config : unconfig
> @$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn diff
> --git a/board/netstar/nand.c b/board/netstar/nand.c index
> 7852365..eea7455 100644
> --- a/board/netstar/nand.c
> +++ b/board/netstar/nand.c
> @@ -45,23 +45,12 @@ static void netstar_nand_hwcontrol(struct
> mtd_info *mtd, int cmd)
> this->IO_ADDR_W = (void *) IO_ADDR_W;
> }
>
> -/*
> - * chip R/B detection
> - */
> -/***
> -static int netstar_nand_ready(struct mtd_info *mtd) -{
> - return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02;
> -}
> -***/
> -
> int board_nand_init(struct nand_chip *nand) {
> nand->options = NAND_SAMSUNG_LP_OPTIONS;
> nand->eccmode = NAND_ECC_SOFT;
> nand->hwcontrol = netstar_nand_hwcontrol;
> -/* nand->dev_ready = netstar_nand_ready; */
> - nand->chip_delay = 18;
> + nand->chip_delay = 400;
> return 0;
> }
> #endif
>
> diff --git a/include/configs/netstar.h
> b/include/configs/netstar.h index 697796a..1a685df 100644
> --- a/include/configs/netstar.h
> +++ b/include/configs/netstar.h
> @@ -48,14 +48,14 @@
> #define CONFIG_SETUP_MEMORY_TAGS 1
> #define CONFIG_INITRD_TAG 1
>
> -#define CFG_DEVICE_NULLDEV 1 /* enable null device */
> #define CONFIG_SILENT_CONSOLE 1 /*
> enable silent startup */
> -
> +#define CFG_CONSOLE_INFO_QUIET
> /*
> * Physical Memory Map
> */
> #define CONFIG_NR_DRAM_BANKS 1 /* we have 1
> bank of DRAM */
> #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
> +#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
> #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
>
> /*
> @@ -63,30 +63,21 @@
> */
> #define CFG_FLASH_BASE PHYS_FLASH_1
> #define CFG_MAX_FLASH_BANKS 1
> -#if (PHYS_SDRAM_1_SIZE == SZ_32M)
> -/*#if 1*/
> -#define CFG_FLASH_CFI /* Flash is CFI
> conformant */
> -#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
> -#define CFG_FLASH_EMPTY_INFO
> -#define CFG_MAX_FLASH_SECT 128
> -#else
> -#define PHYS_FLASH_1_SIZE SZ_1M
> +#define PHYS_FLASH_1_SIZE (1 * 1024 * 1024)
> #define CFG_MAX_FLASH_SECT 19
> #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */
> #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ)
> -#endif
>
> #define CFG_MONITOR_BASE PHYS_FLASH_1
> -#define CFG_MONITOR_LEN SZ_256K
> +#define CFG_MONITOR_LEN (256 * 1024)
>
> /*
> * Environment settings
> */
> #define CFG_ENV_IS_IN_FLASH
> -#define ENV_IS_SOLITARY
> #define CFG_ENV_ADDR 0x4000
> -#define CFG_ENV_SIZE SZ_8K
> -#define CFG_ENV_SECT_SIZE SZ_8K
> +#define CFG_ENV_SIZE (8 * 1024)
> +#define CFG_ENV_SECT_SIZE (8 * 1024)
> #define CFG_ENV_ADDR_REDUND 0x6000
> #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
> #define CONFIG_ENV_OVERWRITE
> @@ -95,14 +86,12 @@
> * Size of malloc() pool
> */
> #define CFG_GBL_DATA_SIZE 128 /* size in bytes
> reserved for initial data */
> -/* XXX #define CFG_MALLOC_LEN (SZ_64K -
> CFG_GBL_DATA_SIZE)*/
> -#define CFG_MALLOC_LEN SZ_4M
> +#define CFG_MALLOC_LEN (4 * 1024 * 1024)
>
> /*
> * The stack size is set up in start.S using the settings below
> */
> -/* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */
> -#define CONFIG_STACKSIZE SZ_1M /* regular stack */
> +#define CONFIG_STACKSIZE (1 * 1024 * 1024) /*
> regular stack */
>
> /*
> * Hardware drivers
> @@ -132,36 +121,25 @@
> #define CFG_MAX_NAND_DEVICE 1
> #define NAND_MAX_CHIPS 1
> #define CFG_NAND_BASE 0x04000000 + (2 << 23)
> +#define NAND_ALLOW_ERASE_ALL 1
>
> /*
> - * JFFS2 partitions (mtdparts command line support)
> + * partitions (mtdparts command line support)
> */
> #define CONFIG_JFFS2_CMDLINE
> #define MTDIDS_DEFAULT
> "nor0=omapflash.0,nand0=omapnand.0"
> -#define MTDPARTS_DEFAULT
> "mtdparts=omapflash.0:8k at 16k(env),8k(r_env),448k at 576k(u-boot);
omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
> +#define MTDPARTS_DEFAULT "mtdparts=" \
> + "omapflash.0:8k at 16k(env),8k(r_env),448k at 576k(u-boot);" \
> +
> "omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
>
> -#if 0
> -#define CONFIG_COMMANDS (CFG_CMD_BDI | \
> - CFG_CMD_BOOTD | \
> - CFG_CMD_DHCP | \
> - CFG_CMD_ENV | \
> - CFG_CMD_FLASH | \
> - CFG_CMD_IMI | \
> - CFG_CMD_LOADB | \
> - CFG_CMD_NET | \
> - CFG_CMD_MEMORY | \
> - CFG_CMD_PING | \
> - CFG_CMD_RUN)
> -
> -#else
> #define CONFIG_COMMANDS (CFG_CMD_BDI | \
> CFG_CMD_BOOTD | \
> CFG_CMD_DHCP | \
> CFG_CMD_ENV | \
> CFG_CMD_FLASH | \
> + CFG_CMD_JFFS2 | \
> CFG_CMD_NAND | \
> CFG_CMD_IMI | \
> - CFG_CMD_JFFS2 | \
> CFG_CMD_LOADB | \
> CFG_CMD_NET | \
> CFG_CMD_MEMORY | \
> @@ -169,7 +147,6 @@
> CFG_CMD_RUN)
>
> #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
> -#endif
>
> #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
> #define CONFIG_LOOPW
> @@ -181,36 +158,31 @@
> #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
> #undef CONFIG_BOOTARGS /* the boot command
> will set bootargs*/
> #define CFG_AUTOLOAD "n" /* No autoload */
> -#define CONFIG_BOOTCOMMAND "run nboot"
> +#define CONFIG_BOOTCOMMAND "run fboot"
> #define CONFIG_PREBOOT "run setup"
> #define CONFIG_EXTRA_ENV_SETTINGS
> \
> + "autostart=yes\0" \
> + "ospart=0\0" \
> "setup=setenv bootargs console=ttyS0,$baudrate " \
> "$mtdparts\0" \
> - "ospart=0\0" \
> "setpart=" \
> "if test -n $swapos; then " \
> - "if test $ospart -eq 0; then chpart nand0,1;
> else chpart nand0,0; fi; "\
> "setenv swapos; saveenv; " \
> - "else " \
> - "chpart nand0,$ospart; " \
> + "if test $ospart -eq 0; then setenv ospart 1;
> else setenv ospart 0;
> +fi; "\
> "fi\0" \
> "nfsargs=setenv bootargs $bootargs " \
>
> "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
> "nfsroot=$rootpath root=/dev/nfs\0" \
> "flashargs=run setpart;setenv bootargs $bootargs " \
> - "root=/dev/mtdblock$partition ro " \
> + "root=mtd:rootfs$ospart ro " \
> "rootfstype=jffs2\0" \
> - "initrdargs=setenv bootargs $bootargs " \
> -
> "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
> - "iboot=bootp;run initrdargs;tftp;bootm\0" \
> - "fboot=run flashargs;fsload /boot/uImage;bootm\0" \
> - "nboot=bootp;run nfsargs;tftp;bootm\0"
> + "fboot=run flashargs;nboot kernel$ospart\0" \
> + "nboot=bootp;run nfsargs;tftp\0"
>
> #if 0 /* feel free to disable for development */
> #define CONFIG_AUTOBOOT_KEYED /* Enable
> password protection */
> -#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot
> in %d sec...\n"
> -#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st
> "password" */
> -#define CONFIG_BOOT_RETRY_TIME 30
> +#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot
> in %d secs...\n"
> +#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st
> "password" */
> #endif
>
> /*
> @@ -228,7 +200,8 @@
> #define CONFIG_AUTO_COMPLETE
>
> #define CFG_MEMTEST_START PHYS_SDRAM_1
> -#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
> +#define CFG_MEMTEST_END PHYS_SDRAM_1 +
> PHYS_SDRAM_1_SIZE - \
> + (CFG_MONITOR_LEN +
> CFG_MALLOC_LEN + CONFIG_STACKSIZE)
>
> #undef CFG_CLKS_IN_HZ /* everything, incl
> board info, in Hz */
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2007-05-24 15:46 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2005-11-03 12:07 [U-Boot-Users] [PATCH] Update board NetStar Ladislav Michl
2006-07-22 19:07 ` Wolfgang Denk
-- strict thread matches above, loose matches on Subject: below --
2007-05-24 15:21 Ladislav Michl
2007-05-24 15:46 ` Peter Pearse
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox