From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stefan Roese <sr@denx.de>
Date: Fri, 7 Apr 2006 03:51:05 +0200
Subject: [U-Boot-Users] ppc4xx: Initializing GPIO0_OR and GPIO0_ODR
In-Reply-To: <44359D8B.9030006@orkun.us>
References: <44359D8B.9030006@orkun.us>
Message-ID: <200604070351.06318.sr@denx.de>
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To: u-boot@lists.denx.de

Hi Tolunay,

On Friday, 7. April 2006 01:00, Tolunay Orkun wrote:
> On a PPC405EP based boards, U-Boot is initializing below registers to
> select between primary and alternate functions of the GPIO pins (e.g.
> GPIO10 vs CS1) using the CFG_CPIO0_... macros defined in the board
> config file.
>
> GPIO0_TCR, GPIO0_OSRH, GPIO0_OSRL, GPIO0_TSRH, GPIO0_TSRL, GPIO0_ISR1H,
> GPIO0_ ISR1L
>
> This much is sufficient for alternate function programming. However, if
> a the GPIO pin is actually used as GPIO output pin, the initial signal
> level presented happens to be "0" which may not be appropriate for some
> implementations.
>
> I propose to introduce CFG_GPIO0_OR and CFG_CPIO0_ODR macros that could
> be defined in the appropriate board config file and initialize GPIO0_OR
> and GPIO0_ODR before GPIO0_TCR. If these macros are undefined the
> existing code behavior could be maintained so the additional macros
> would not break any existing board or add any additional code.

Sounds good to me.

> I will be introducing a patch to take care of this but I wanted to get
> feedback first.

Please send your patch.

Best regards,
Stefan

PS: Did you happen to take a look at the recent changes I made to the 
cfi_flash driver? Now the Intel "legacy lock/unlocking" is supported. Please 
let me know if you see any problems with these changes (I could only test on 
J3 FLASH's with legacy unlocking).