[U-Boot-Users] Incorrect exception reporting for PPC405 in Xilinx VirtexII Pro FPGAs?

[U-Boot-Users] Incorrect exception reporting for PPC405 in Xilinx VirtexII Pro FPGAs?

[Keith J Outwater]

Hello all,
I am trying to debug a hardware problem involving a peripheral interface 
in a system that uses the PPC405 inside a Xilinx Virtex II Pro FPGA.
When the peripheral device does not respond and the PLB (Processor Local 
Bus) to OPB (On-chip Peripheral Bus) bridge times out, U-Boot reports a 
bus fault:

Bus Fault @ 0x03fc7500, fixup 0x00000000
Machine check in kernel mode.
Caused by (from msr): regs 03f6fc80 Data parity signal
NIP: 03FC7500 XER: 20000000 LR: 03FB3A70 REGS: 03f6fc80 TRAP: 0200 DAR: 
00FB1000
MSR: 00029000 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 03FB3A64 03F6FD70 FFFECCB0 03FE0B7C 00000000 00000010 FFFFFFF4 
00000007
GPR08: 00000000 00000020 00000000 FFFFFFFF 00000020 FFFED040 03FF1A00 
00FB1000
GPR16: 00000000 00000000 00000000 0000000B 00000000 00000000 00000001 
00000000
GPR24: 00000000 00000000 00000000 00000000 8080C008 03F6FF58 03FF1A24 
03F712D8
Call backtrace:
machine check
### ERROR ### Please RESET the board ###
 
Note that the cause is listed as "Data parity signal".  This appears to be 
a result of this code in ./cpu/ppc4xx/traps.c:

void
MachineCheckException(struct pt_regs *regs)
{
        unsigned long fixup;

        /* Probing PCI using config cycles cause this exception
         * when a device is not present.  Catch it and return to
         * the PCI exception handler.
         */
        if ((fixup = search_exception_table(regs->nip)) != 0) {
                regs->nip = fixup;
                return;
        }

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
        if (debugger_exception_handler && 
(*debugger_exception_handler)(regs))
                return;
#endif

        printf("Machine check in kernel mode.\n");
        printf("Caused by (from msr): ");
        printf("regs %p ",regs);
        switch( regs->msr & 0x000F0000) {
        case (0x80000000>>12):
                printf("Machine check signal - probably due to mm fault\n"
                       "with mmu off\n");
                break;
        case (0x80000000>>13):
                printf("Transfer error ack signal\n");
                break;
        case (0x80000000>>14):
                printf("Data parity signal\n");
                break;
        case (0x80000000>>15):
                printf("Address parity signal\n");
                break;
        default:
                printf("Unknown values in msr\n");
        }
        show_regs(regs);
        print_backtrace((unsigned long *)regs->gpr[1]);
        panic("machine check");
}

In the function above, the cause of the exception is being inferred from 
the msr, but according to the Xilinx documentation (PowerPC Processor 
Reference Guide, EDK 6.1, September 2, 2003), the msr does not provide 
this information.  In fact, it is the ESR (Exception Syndrome Register) 
that indicated the cause of the exception.

I checked, and it does not appear that this register is provided in the 
pt_regs struct.

So now to my question:  Am I on the right track here?  Has anyone else 
looked at this and fixed this code if it is in fact broken?  If it needs 
fixing, can anyone provide some pointers?

BTW, I am using a reasonably (< 3 week old) U-Boot from the Denx git 
repository.

Thanks!
Keith
 

[U-Boot-Users] Incorrect exception reporting for PPC405 in Xilinx VirtexII Pro FPGAs?

[Stefan Roese]

Hi Keith,

On Wednesday 30 August 2006 20:07, Keith J Outwater wrote:
> In the function above, the cause of the exception is being inferred from
> the msr, but according to the Xilinx documentation (PowerPC Processor
> Reference Guide, EDK 6.1, September 2, 2003), the msr does not provide
> this information.  In fact, it is the ESR (Exception Syndrome Register)
> that indicated the cause of the exception.

Good catch.

> I checked, and it does not appear that this register is provided in the
> pt_regs struct.
>
> So now to my question:  Am I on the right track here?  Has anyone else
> looked at this and fixed this code if it is in fact broken?  If it needs
> fixing, can anyone provide some pointers?

You seem to be right here. So we (you) need to fix this routine to use the 
correct register (ESR) with the correct bits. Best would be, if you could 
provide a patch. A patch against your 3 weeks old U-Boot version is ok, since 
this file didn't change for a quite long time. And please also provide a 
CHANGELOG entry.

Thanks.

Best regards,
Stefan

[U-Boot-Users] Incorrect exception reporting for PPC405 in Xilinx VirtexII Pro FPGAs?

[Keith J Outwater]

Stefan Roese <sr@denx.de> wrote on 08/31/2006 02:39:17 AM:

> Hi Keith,
> 
> On Wednesday 30 August 2006 20:07, Keith J Outwater wrote:
> > In the function above, the cause of the exception is being inferred 
from
> > the msr, but according to the Xilinx documentation (PowerPC Processor
> > Reference Guide, EDK 6.1, September 2, 2003), the msr does not provide
> > this information.  In fact, it is the ESR (Exception Syndrome 
Register)
> > that indicated the cause of the exception.
> 
> Good catch.
> 
> > I checked, and it does not appear that this register is provided in 
the
> > pt_regs struct.
> >
> > So now to my question:  Am I on the right track here?  Has anyone else
> > looked at this and fixed this code if it is in fact broken?  If it 
needs
> > fixing, can anyone provide some pointers?
> 
> You seem to be right here. So we (you) need to fix this routine to use 
the 
> correct register (ESR) with the correct bits. Best would be, if you 
could 
> provide a patch. A patch against your 3 weeks old U-Boot version is ok, 
since 
> this file didn't change for a quite long time. And please also provide a 

> CHANGELOG entry.

OK. I'll take a crack at fixing it.  It looks like the biggest issue will 
be
how to add the ppc405 specific registers to the pt_regs struct.

I'm also going to add (configurable) support for dumping the error 
information
registers in the Xilinx PLB2OPB bridge.

Keith

> 
> Thanks.
> 
> Best regards,
> Stefan