From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] DCR register read/write for PPC440EP
Date: Thu, 28 Sep 2006 14:54:41 +0200 [thread overview]
Message-ID: <200609281454.42189.sr@denx.de> (raw)
In-Reply-To: <406A31B117F2734987636D6CCC93EE3C04380F@ehost011-3.exch011.intermedia.net>
Hi Leonid,
On Wednesday 27 September 2006 18:06, Leonid wrote:
> I'm trying to read certain configuration register (SDR0_PINSTP) using
> u-boot setdcr/getdcr commands (I run 1.1.4 u-boot on AMCC PPC440EP
> Yosemite board). First thing I do is setting this register's offset
> (0x40) in the SDR0_CFGADDR (0xE) DCRN:
>
> => setdcr e
> 000e: 00000020 ? 40
> 000e: 00000040 ?
> =>
>
> However it doesn't look having any effect:
>
> => getdcr e
> 000e: 00000020
I seems to be overwritten in the meantime. A look at the 440EP manual shows,
that DCR reg 0x20 is the CPR0_CLKUPD register, which is most likely accessed
each ms in the 440 timer interrupt (didn't check though).
What you really need, is an U-Boot command to set/get SDR registers,
indirectly accessed via the DCR 0x0e/0x0f registers. Something
like "setsdr/getsdr". It would be best, if you could supply a proper patch
with such additional commands. Thanks.
Best regards,
Stefan
next prev parent reply other threads:[~2006-09-28 12:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-09-27 16:06 [U-Boot-Users] DCR register read/write for PPC440EP Leonid
2006-09-28 12:54 ` Stefan Roese [this message]
2006-09-28 16:58 ` Leonid
2006-09-28 18:44 ` Stefan Roese
2006-09-28 21:54 ` Leonid
2006-09-30 2:13 ` Stefan Roese
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