From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stefan Roese <sr@denx.de>
Date: Thu, 28 Sep 2006 14:54:41 +0200
Subject: [U-Boot-Users] DCR register read/write for PPC440EP
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References: <406A31B117F2734987636D6CCC93EE3C04380F@ehost011-3.exch011.intermedia.net>
Message-ID: <200609281454.42189.sr@denx.de>
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To: u-boot@lists.denx.de

Hi Leonid,

On Wednesday 27 September 2006 18:06, Leonid wrote:
> I'm trying to read certain configuration register (SDR0_PINSTP) using
> u-boot setdcr/getdcr commands (I run 1.1.4 u-boot on AMCC PPC440EP
> Yosemite board). First thing I do is setting this register's offset
> (0x40) in the SDR0_CFGADDR (0xE) DCRN:
>
> => setdcr e
> 000e: 00000020 ? 40
> 000e: 00000040 ?
> =>
>
> However it doesn't look having any effect:
>
> => getdcr e
> 000e: 00000020

I seems to be overwritten in the meantime. A look at the 440EP manual shows, 
that DCR reg 0x20 is the CPR0_CLKUPD register, which is most likely accessed 
each ms in the 440 timer interrupt (didn't check though).

What you really need, is an U-Boot command to set/get SDR registers, 
indirectly accessed via the DCR 0x0e/0x0f registers. Something 
like "setsdr/getsdr". It would be best, if you could supply a proper patch 
with such additional commands. Thanks.

Best regards,
Stefan