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* [U-Boot-Users] DCR register read/write for PPC440EP
@ 2006-09-27 16:06 Leonid
  2006-09-28 12:54 ` Stefan Roese
  0 siblings, 1 reply; 6+ messages in thread
From: Leonid @ 2006-09-27 16:06 UTC (permalink / raw)
  To: u-boot

Hi,

I'm trying to read certain configuration register (SDR0_PINSTP) using
u-boot setdcr/getdcr commands (I run 1.1.4 u-boot on AMCC PPC440EP
Yosemite board). First thing I do is setting this register's offset
(0x40) in the SDR0_CFGADDR (0xE) DCRN:

=> setdcr e
000e: 00000020 ? 40
000e: 00000040 ? 
=> 

However it doesn't look having any effect:

=> getdcr e
000e: 00000020

And when I read SDR0_CFGDATA (0xF), I get register with offset 0x20
(SDR0_SDSTP0) as expected:

=> getdcr f
000f: 8570828a

Before I start to debug do_setdcr() function, may be somebody knows this
issue and it was even fixed?

Thanks,

Leonid.

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2006-09-30  2:13 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2006-09-27 16:06 [U-Boot-Users] DCR register read/write for PPC440EP Leonid
2006-09-28 12:54 ` Stefan Roese
2006-09-28 16:58   ` Leonid
2006-09-28 18:44     ` Stefan Roese
2006-09-28 21:54       ` Leonid
2006-09-30  2:13         ` Stefan Roese

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