From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Sun, 1 Oct 2006 11:23:06 +0200 Subject: [U-Boot-Users] (no subject) In-Reply-To: References: Message-ID: <200610011123.07326.sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Gerald, On Sunday 01 October 2006 05:04, Gerald Jackson wrote: > I made the change that Marc suggested and still no luck. If both dimms > are in use the system hangs Hangs where? Also upon SDRAM initialization? > and if only the second Dimm slot is in use I > get: > > U-Boot 1.1.4 (Sep 30 2006 - 10:08:43) > > CPU: AMCC PowerPC 440GX Rev. F at 800 MHz (PLB=160, OPB=80, EBC=40 > MHz) > I2C boot EEPROM enabled > Internal PCI arbiter enabled > 32 kB I-Cache 32 kB D-Cache > Board: Ocotea - AMCC PPC440GX Evaluation Board > I2C: ready > DRAM: ERROR: Cannot determine a common read delay. > ### ERROR ### Please RESET the board ### > > Any Ideals? Ideals? Not really. But I have an idea! ;-) How did you get the Board? Directly from AMCC? Did it never work at all? Your PLB frequency seems strange to me (160MHz). Please try to configure your Ocotea to use a different setup, for example 533MHz CPU and 133MHz PLB. Here is the output from our Ocotea: U-Boot 1.1.4-g887e2ec9-dirty (Sep 7 2006 - 11:55:16) CPU: AMCC PowerPC 440GX Rev. F at 533.333 MHz (PLB=133, OPB=66, EBC=66 MHz) I2C boot EEPROM enabled Bootstrap Option F - Boot ROM Location I2C (Addr 0x54) Internal PCI arbiter enabled 32 kB I-Cache 32 kB D-Cache Board: Ocotea - AMCC PPC440GX Evaluation Board I2C: ready DRAM: 256 MB FLASH: 5 MB PCI: Bus Dev VenId DevId Class Int 00 01 8086 107c 0200 00 In: serial Out: serial Err: serial Net: ppc_4xx_eth0, ppc_4xx_eth1, ppc_4xx_eth2, ppc_4xx_eth3 Type "run flash_nfs" to mount root filesystem over NFS Hit any key to stop autoboot: 0 => Best regards, Stefan