[U-Boot-Users] DDR SDRAM in DIMM module for Yosemite-like PPC440EP board.

[U-Boot-Users] DDR SDRAM in DIMM module for Yosemite-like PPC440EP board.

[Leonid]

Hi:

I'm trying to port u-boot for "Yosemite-like" board with AMCC PPC440EP
CPU. The difference between this board and Yosemite itself is that it
has 4 128M banks of DDR SDRAM instead of 2 and (which is probably more
important) these chips are on DIMM module. I think I've configured
everything correct, see SDRAM registers block from BDI2000 config file
below:

; Setup SDRAM Controller (DDR SDRAM)
WDCR    0x10    0x00000082      ;Select SDRAM0_CLKTR
WDCR    0x11    0x40000000      ;CLKTR: Advance 90 degrees
WDCR    0x10    0x00000080      ;Select SDRAM0_TR0
WDCR    0x11    0x410a4012      ;TR0:
WDCR    0x10    0x00000081      ;Select SDRAM0_TR1
WDCR    0x11    0x80800819      ;TR1:
WDCR    0x10    0x00000040      ;Select SDRAM0_B0CR
;;WDCR  0x11    0x000a4001      ;B0CR: 128M first bank, start 0x0, 13x10
WDCR    0x11    0x000a6001      ;B0CR: 128M first bank, start 0x0, 13x11
WDCR    0x10    0x00000044      ;Select SDRAM0_B1CR
;;WDCR  0x11    0x080a4001      ;B1CR: 128M second bank, start
0x08000000, 13x10
WDCR    0x11    0x080a6001      ;B1CR: 128M second bank, start
0x08000000, 13x11
WDCR    0x10    0x00000048      ;Select SDRAM0_B2CR
WDCR    0x11    0x100a6001      ;B2CR: 128M third bank, start
0x10000000, 13x11
WDCR    0x10    0x0000004C      ;Select SDRAM0_B3CR
WDCR    0x11    0x180a6001      ;B3CR: 128M forth bank, start
0x18000000, 13x11
WDCR    0x10    0x00000030      ;Select SDRAM0_RTR
WDCR    0x11    0x04080000      ;RTR:
WDCR    0x10    0x00000020      ;Select SDRAM0_CFG0
WDCR    0x11    0x36000000      ;CFG0: 32bit, PMU disable, DIMM enable.
WDCR    0x11    0x86000000      ;CFG0: enable SDRAM & DIMM
WDCR    0x10    0x00000021      ;Select SDRAM0_CFG1
WDCR    0x11    0x00000000      ;CFG1

However MRSC bit of SDRAM0_MCSTS register never gets set meaning SDRAM
controller has never successfully completed the Mode Register Set
Command. Attempts to read memory also fail (from BDI2000 itself and from
u-boot where I've modified memory configuration of course).

That can be HW problem of course, but may be somebody can suggest any
configuration problem leading to similar symptoms? Any ideas at all?

Thanks,

Leonid.

[U-Boot-Users] DDR SDRAM in DIMM module for Yosemite-like PPC440EP board.

[Stefan Roese]

Hi Leonid,

On Friday 20 October 2006 08:30, Leonid wrote:
> I'm trying to port u-boot for "Yosemite-like" board with AMCC PPC440EP
> CPU. The difference between this board and Yosemite itself is that it
> has 4 128M banks of DDR SDRAM instead of 2 and (which is probably more
> important) these chips are on DIMM module.

If you are using DIMM modules, please don't use the board specific DDR init 
code of the Yosemite, but the cpu specific DDR init code f?r DDR DIMM 
modules, like the other 440 AMCC eval boards do (e.g. ocotea, bamboo).

> I think I've configured 
> everything correct, see SDRAM registers block from BDI2000 config file
> below:
>
> ; Setup SDRAM Controller (DDR SDRAM)
> WDCR    0x10    0x00000082      ;Select SDRAM0_CLKTR

<snip>

> However MRSC bit of SDRAM0_MCSTS register never gets set meaning SDRAM
> controller has never successfully completed the Mode Register Set
> Command. Attempts to read memory also fail (from BDI2000 itself and from
> u-boot where I've modified memory configuration of course).

Please modify your U-Boot configuration to use the cpu/ppc4xx/spd_sdram.c 
code. The following lines should be added to your board config file (with the 
correct I2C addresses of course):

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM       1        /* Use SPD EEPROM for setup     */
#define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */

> That can be HW problem of course, but may be somebody can suggest any
> configuration problem leading to similar symptoms? Any ideas at all?

Yes, a HW problem is also possible. What termination are you using? Did 
you "clone" the HW design from some IBM/AMCC eval boards?

Best regards,
Stefan

[U-Boot-Users] DDR SDRAM in DIMM module for Yosemite-like PPC440EP board.

[Leonid]

On Friday, October 20, 2006 4:59 AM Stefan Roese wrote:
> If you are using DIMM modules, please don't use the board specific DDR 
> init code of the Yosemite, but the cpu specific DDR init code f?r DDR DIMM 
> modules, like the other 440 AMCC eval boards do (e.g. ocotea, bamboo).

[Leonid] I'll try to do that, thank you. Yet I probably didn't make myself clear: I connect BDI2000 first whose configuration file can initialize all registers (though one can skip directly to code by "reset run" BDI command). Neither code is running in this moment (except BDI's firmware) and I expect that if BDI config file is correct, SDRAM will be available even BEFORE u-boot code takes over, but it's not: Mode Register Set Command never get completed and WORKSPACE command from config file doesn't work. I'll take a look into BDI config files for other AMCC boards - like ocotea & bamboo if I'll be able to find them.
 
> Please modify your U-Boot configuration to use the cpu/ppc4xx/spd_sdram.c 
> code. The following lines should be added to your board config file (with 
> the correct I2C addresses of course):

> #define CONFIG_SPD_EEPROM     1        /* Use SPD EEPROM for setup     */
> #define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */

[Leonid] You mean to use option G or H to read bootstrap from serial EEPROM? Or some another exercise with EEPROM I must do because I'm using DIMM module? I'll read this code to see what it does.

> Yes, a HW problem is also possible. What termination are you using? Did 
> you "clone" the HW design from some IBM/AMCC eval boards?
[Leonid] The board was supposed to be cloned from Yosemite so it was complete surprise for me when I learnt that HW folks put memory into DIMM module. Can you recommend what exactly should I ask them to look into - what "termination" do you mean? 

Best regards,
Leonid.

[U-Boot-Users] DDR SDRAM in DIMM module for Yosemite-like PPC440EP board.

[Ben Warren]

On Fri, 2006-10-20 at 08:57 -0700, Leonid wrote:
> On Friday, October 20, 2006 4:59 AM Stefan Roese wrote:
> > If you are using DIMM modules, please don't use the board specific DDR 
> > init code of the Yosemite, but the cpu specific DDR init code f?r DDR DIMM 
> > modules, like the other 440 AMCC eval boards do (e.g. ocotea, bamboo).
> 
> [Leonid] I'll try to do that, thank you. Yet I probably didn't make myself clear: I connect BDI2000 first whose configuration file can initialize all registers (though one can skip directly to code by "reset run" BDI command). Neither code is running in this moment (except BDI's firmware) and I expect that if BDI config file is correct, SDRAM will be available even BEFORE u-boot code takes over, but it's not: Mode Register Set Command never get completed and WORKSPACE command from config file doesn't work. I'll take a look into BDI config files for other AMCC boards - like ocotea & bamboo if I'll be able to find them.
>  
> > Please modify your U-Boot configuration to use the cpu/ppc4xx/spd_sdram.c 
> > code. The following lines should be added to your board config file (with 
> > the correct I2C addresses of course):
> 
> > #define CONFIG_SPD_EEPROM     1        /* Use SPD EEPROM for setup     */
> > #define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */
> 
> [Leonid] You mean to use option G or H to read bootstrap from serial EEPROM? Or some another exercise with EEPROM I must do because I'm using DIMM module? I'll read this code to see what it does.
> 
SPD_EEPROM is not a bootstrap EEPROM.  It's an I2C eeprom on the DIMM
itself that is filled in by the manufacturer to include all sorts of
timing and configuration information.  You should use this whenever
possible because in theory it makes DDR DIMMs plug & play.  This of
course assumes that your controller is wired and laid out properly and
that your spd_eeprom parsing code works...

regards,
Ben

[U-Boot-Users] DDR SDRAM in DIMM module for Yosemite-likePPC440EP board.

[Leonid]

On Friday, October 20, 2006 9:04 AM Ben Warren wrote:

> SPD_EEPROM is not a bootstrap EEPROM.  It's an I2C eeprom on the DIMM
> itself that is filled in by the manufacturer to include all sorts of
> timing and configuration information.  You should use this whenever
> possible because in theory it makes DDR DIMMs plug & play.  This of
> course assumes that your controller is wired and laid out properly and
> that your spd_eeprom parsing code works...

[Leonid] I see, that may be it - this way u-boot may be workable. Is it
the only way to work with DIMM module? How I can initialize such SDRAM
inside BDI2000 config file? Because I cannot use WORKSPACE otherwise and
code burning takes long time... 

Regards,
Leonid.

[U-Boot-Users] DDR SDRAM in DIMM module for Yosemite-likePPC440EP board.

[Ben Warren]

On Fri, 2006-10-20 at 09:23 -0700, Leonid wrote:
> On Friday, October 20, 2006 9:04 AM Ben Warren wrote:
> 
> > SPD_EEPROM is not a bootstrap EEPROM.  It's an I2C eeprom on the DIMM
> > itself that is filled in by the manufacturer to include all sorts of
> > timing and configuration information.  You should use this whenever
> > possible because in theory it makes DDR DIMMs plug & play.  This of
> > course assumes that your controller is wired and laid out properly and
> > that your spd_eeprom parsing code works...
> 
> [Leonid] I see, that may be it - this way u-boot may be workable. Is it
> the only way to work with DIMM module? How I can initialize such SDRAM
> inside BDI2000 config file? Because I cannot use WORKSPACE otherwise and
> code burning takes long time... 

Of course you don't have to use the SPD stuff, but you should.  If the
BDI won't work as-is, you need to learn more about your DDR controller
and your particular DIMM's timing information, both of which should be
readily available.  While DDR control is fairly complicated, there
aren't that many knobs to turn and you may get lucky early on.

Another approach that's less systematic is to get U-boot working, dump
the DDR controller register contents and use those in your BDI config
file.  This will involve a few painful workspace-less flash burns,
though...  You can save a bit of pain by stripping your U-boot image to
bare-bones.

Sorry there's no easier answer, but if your hardware is wired right
you'll probably nail this quickly.

regards,
Ben

[U-Boot-Users] DDR SDRAM in DIMM module for Yosemite-likePPC440EP board.

[Stefan Roese]

On Friday 20 October 2006 18:50, Ben Warren wrote:
> > [Leonid] I see, that may be it - this way u-boot may be workable. Is it
> > the only way to work with DIMM module? How I can initialize such SDRAM
> > inside BDI2000 config file? Because I cannot use WORKSPACE otherwise and
> > code burning takes long time...
>
> Of course you don't have to use the SPD stuff, but you should.  If the
> BDI won't work as-is, you need to learn more about your DDR controller
> and your particular DIMM's timing information, both of which should be
> readily available.  While DDR control is fairly complicated, there
> aren't that many knobs to turn and you may get lucky early on.
>
> Another approach that's less systematic is to get U-boot working,

Yes. When your hardware layout is ok, you have a good chance that with the 
correct setup (I2C SPD EEPROM addresses), U-Boot will initialize the DDR 
controller correctly. Then you have no need to burn flash via the debugger 
anymore. ;-)

Best regards,
Stefan

[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Leonid]

On Friday, October 20, 2006 9:50 AM Ben Warren wrote:
> Of course you don't have to use the SPD stuff, but you should.  

[Leonid] Unfortunately SPD stuff is out of question - on our board
UDIMM's EEPROM is not connected to CPU I2C bus.

> If the
> BDI won't work as-is, you need to learn more about your DDR controller
> and your particular DIMM's timing information, both of which should be
> readily available.  While DDR control is fairly complicated, there
> aren't that many knobs to turn and you may get lucky early on.

[Leonid] That what I'm going to do. I have datasheet, the module name is
MT8VDDT12832U. If somebody from this community happens to have BDI or
u-boot configuration for such or similar module, I'll appreciate that
information.

> Another approach that's less systematic is to get U-boot working, dump
> the DDR controller register contents and use those in your BDI config
> file.  

[Leonid] I'm familiar with this method - I used it to get BDI work with
some ARM board. Yet as you said I must have u-boot working with this
DIMM first and provided I don't have SPD option it will probably require
exactly the same effort as BDI configuration - configure all registers
properly manually.

> This will involve a few painful workspace-less flash burns,
> though...  You can save a bit of pain by stripping your U-boot image
to
> bare-bones.

[Leonid] It's not that bad actually - takes less than 2 minutes to burn
entire 512KB u-boot image together with flash erasing even without
workspace. But as I see now I may as well concentrate on BDI config file
- exactly same registers must be configured - without touching u-boot
code at all for the time being.

> Sorry there's no easier answer, but if your hardware is wired right
> you'll probably nail this quickly.

[Leonid] I do appreciate your help, thanks a lot.

Regards,
Leonid.

[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Stefan Roese]

On Friday 20 October 2006 20:02, Leonid wrote:
> On Friday, October 20, 2006 9:50 AM Ben Warren wrote:
> > Of course you don't have to use the SPD stuff, but you should.
>
> [Leonid] Unfortunately SPD stuff is out of question - on our board
> UDIMM's EEPROM is not connected to CPU I2C bus.

Whow. Never seen this one. So your only chance is to _always_ use the same (or 
compatible) DIMM module in your board and configure the controller for it.

Best regards,
Stefan

[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Leonid]

On Friday, October 20, 2006 11:33 AM Stefan Roese
> Whow. Never seen this one. So your only chance is to _always_ use the
same > (or compatible) DIMM module in your board and configure the
controller for 
> it.

They actually hook it up now, so I may have EEPROM after all. I've
learnt that another PPC440EP board - "bamboo" - has exactly this DIMM
module, so I now have kind of mix of Yosemite and Bamboo. Do you think I
shall go with standard spd_sdram.c or manually port code from bamboo.c
to Yosemite.c?

Also does somebody happen to have BDI2000 config file for bamboo board -
I couldn't find one...

Best regards,
Leonid.

[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Stefan Roese]

On Friday 20 October 2006 20:47, Leonid wrote:
> They actually hook it up now, so I may have EEPROM after all. I've learnt
> that another PPC440EP board - "bamboo" - has exactly this DIMM 
> module, so I now have kind of mix of Yosemite and Bamboo. Do you think I
> shall go with standard spd_sdram.c or manually port code from bamboo.c
> to Yosemite.c?

You should go with standard spd_sdram.c (I did mention this before, right?)! 
Just remove your board specific sdram init code and include the definitions I 
mentioned earlier in your board config file.

But please note that bamboo (440EP) is not a perfect example for DDR init on 
440 systems, since it has one bank of DDR soldered onboard _plus_ the DIMM 
module(s).

> Also does somebody happen to have BDI2000 config file for bamboo board -
> I couldn't find one...

Attached is a bamboo config file. But again, this DDR configuration is for the 
onboard SDRAM IIRC.

Best regards,
Stefan
-------------- next part --------------
;bdiGDB configuration file for IBM 440GX Reference Board
; ------------------------------------------------------
;
[INIT]
; Setup TLB
WTLB    0xF0000095  0x0F00003F  ;Boot Space 256MB
WTLB    0x00000094  0x0000003F  ;SDRAM 256MB @ 0x00000000
WTLB    0xd0000095  0x2000001B  ;PCI Page Entry
WTLB    0xe0000095  0x1400001B  ;Peripheral Page Entry
;
; Setup caches
WSPR    0x370   0x00000000      ;INV0
WSPR    0x371   0x00000000      ;INV1
WSPR    0x372   0x00000000      ;INV2
WSPR    0x373   0x00000000      ;INV3
WSPR    0x390   0x00000000      ;DNV0
WSPR    0x391   0x00000000      ;DNV1
WSPR    0x392   0x00000000      ;DNV2
WSPR    0x393   0x00000000      ;DNV3
WSPR    0x398   0x0001f800      ;DVLIM
WSPR    0x399   0x0001f800      ;IVLIM
;
; Setup Peripheral Bus
WDCR	0x12	0x00000010	;Select EBC0_B0AP
WDCR	0x13	0x04055200	;B0AP: Flash and SRAM
WDCR	0x12	0x00000000	;Select EBC0_B0CR
WDCR	0x13	0xffc58000	;B0CR: 4MB at 0xFFC00000, r/w, 8bit
;WDCR	0x13	0xffc5a000	;B0CR: 4MB at 0xFFC00000, r/w, 16bit
;WDCR	0x12	0x00000012	;Select EBC0_B2AP
;WDCR	0x13	0x05055200	;B2AP: 4 MB Flash
;WDCR	0x12	0x00000002	;Select EBC0_B2CR
;WDCR	0x13	0xff838000	;B2CR: 2MB at 0xFFE00000, r/w, 8bit
;
; Setup SDRAM Controller (DDR SDRAM)
WDCR	0x10	0x00000082	;Select SDRAM0_CLKTR
WDCR	0x11	0x40000000	;CLKTR: Advance 90 degrees
WDCR	0x10	0x00000080	;Select SDRAM0_TR0
WDCR	0x11	0x410a4012	;TR0:
WDCR	0x10	0x00000081	;Select SDRAM0_TR1
WDCR	0x11	0x8080080b	;TR1:
WDCR	0x10	0x00000040	;Select SDRAM0_B0CR
WDCR	0x11	0x000a4001	;B0CR:
WDCR	0x10	0x00000044	;Select SDRAM0_B1CR
WDCR	0x11	0x080a4001	;B1CR:
WDCR	0x10	0x00000030	;Select SDRAM0_RTR
WDCR	0x11	0x04080000	;RTR:
WDCR	0x10	0x00000020	;Select SDRAM0_CFG0
WDCR	0x11	0x34000000	;CFG0: enable SDRAM
WDCR	0x11	0x84000000	;CFG0: enable SDRAM
DELAY   100
;
; Setup default vector table
WSPR    0x03f   0x00000000      ;IVPR   vector base at 0x00000000
WSPR    0x190   0x00000100      ;IVOR0  Critical Input
WSPR    0x191   0x00000200      ;IVOR1  Machine Check
WSPR    0x192   0x00000300      ;IVOR2  Data Storage
WSPR    0x193   0x00000400      ;IVOR3  Instruction Storage
WSPR    0x194   0x00000500      ;IVOR4  External Input
WSPR    0x195   0x00000600      ;IVOR5  Alignment
WSPR    0x196   0x00000700      ;IVOR6  Program
WSPR    0x197   0x00000800      ;IVOR7  Reserved
WSPR    0x198   0x00000c00      ;IVOR8  System Call
WSPR    0x199   0x00000a00      ;IVOR9  Reserved
WSPR    0x19a   0x00001000      ;IVOR10 Decrementer
WSPR    0x19b   0x00001010      ;IVOR11 Fixed Interval Timer
WSPR    0x19c   0x00001020      ;IVOR12 Watchdog Timer
WSPR    0x19d   0x00001100      ;IVOR13 Data TLB Error
WSPR    0x19e   0x00001200      ;IVOR14 Instruction TLB Error
WSPR    0x19f   0x00000f00      ;IVOR15 Debug
;
; Clear DBCR1 and DBCR2
WSPR    0x135   0x00000000      ;DBCR1
WSPR    0x136   0x00000000      ;DBCR2


[TARGET]
JTAGCLOCK   0                   ;use 16 MHz JTAG clock
CPUTYPE     440 		;the used target CPU type
SCANMISC    8                   ;IR length is 8 bits for 440GX
WAKEUP      50                  ;wakeup time after reset
BREAKMODE   SOFT      	        ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    JTAG                ;JTAG or HWBP, HWBP uses one or two hardware breakpoints
;MMU         XLAT 0xC0000000     ;enable virtual address mode
;PTBASE      0x00000000          ;address where kernel/user stores pointer to page table
;SIO         7 9600              ;TCP port for serial IO
;REGLIST     ALL                 ;select register to transfer to GDB


[HOST]
IP          192.168.1.1
FILE        /tftpboot/bamboo/u-boot.bin
FORMAT      BIN
DUMP        /tftpboot/bamboo/dump.bin
PROMPT      440EP>


[FLASH]
; user flash at 0xff800000, AM29LV033C (4M x 8)
;WORKSPACE   0xFF800000  ;workspace in SRAM for fast programming algorithm
WORKSPACE   0x00100000  ;workspace in SDRAM for fast programming algorithm
CHIPTYPE    AM29F       ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPSIZE    0x80000     ;The size of one flash chip in bytes
BUSWIDTH    8           ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        /tftpboot/bamboo/u-boot.bin
FORMAT      BIN 0xFFFA0000
;ERASE       0xFFF80000  ;erase sector 4
;ERASE       0xFFF90000  ;erase sector 4
ERASE       0xFFFA0000  ;erase sector 4
ERASE       0xFFFB0000  ;erase sector 4
ERASE       0xFFFC0000  ;erase sector 4
ERASE       0xFFFD0000  ;erase sector 5
ERASE       0xFFFE0000  ;erase sector 6
ERASE       0xFFFF0000  ;erase sector 7

[REGS]
IDCR1	0x010	0x011	;SDRAM0_CFGADDR and SDRAM0_CFGDATA
IDCR2	0x012	0x013	;EBC0_CFGADDR   and EBC0_CFGDATA
IDCR3	0x014	0x015	;EBM0_CFGADDR   and EBM0_CFGDATA
IDCR4	0x016	0x017	;PPM0_CFGADDR   and PPM0_CFGDATA
IDCR5	0x00C	0x00D	;CPR0_CFGADDR   and CPR0_CFGDATA
IDCR6	0x00E	0x00F	;SDR0_CFGADDR   and SDR0_CFGDATA
DMM1    0xD0000000      ;PCI        (should map to 2_000_0000)
DMM2    0xE0000000      ;Peripheral (should map to 1_400_0000)
FILE    /tftpboot/BDI2000/reg440gx.def

[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Stefan Roese]

Hi Leonid,

On Friday 20 October 2006 23:00, Stefan Roese wrote:
> But please note that bamboo (440EP) is not a perfect example for DDR init
> on 440 systems, since it has one bank of DDR soldered onboard _plus_ the
> DIMM module(s).

I just realized that we have another 440EP board in the U-Boot tree that 
matches your SDRAM setup better. The "pcs440ep". It has one DIMM module and 
no onboard SDRAM.

Best regards,
Stefan

[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Leonid]

On Saturday, October 21, 2006 3:19 AM Stefan Roese wrote:
> > But please note that bamboo (440EP) is not a perfect example for DDR

> > init on 440 systems, since it has one bank of DDR soldered onboard 
> > _plus_ the DIMM module(s).

> I just realized that we have another 440EP board in the U-Boot tree
that 
> matches your SDRAM setup better. The "pcs440ep". It has one DIMM
module 
> and no onboard SDRAM.

[Leonid] Actually I could make spd_sdram work for my board (our HW guy
hooked up DIMM EEPROM connections for me). I stepped through code using
debugger and found out that EEPROM (address 0x51 on our board) has been
successfully read, all parameters were sane and SDRAM registers have
been updated accordantly. However sdram0_mcsts register's most
significant bit never becomes 1, meaning SDRAM controller cannot
complete memory initialization and code stays in endless loop:

	/*
	 * wait for SDRAM_CFG0_DC_EN to complete
	 */
	while (1) {
		mfsdram(mem_mcsts, mcsts);
		if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
			break;
		}
	}

That looks like HW problem for me. Of course, I'll look through actual
registers' values more carefully - may be spd_sdram() just parsed EEPROM
parameters wrongly but I doubt that.

Just in case - did you happen to have BDI config file for that board -
brief search in the ftp://ftp.denx.de/pub/BDI2000/ directory didn't
provide results.

Best regards,
Leonid.

[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Stefan Roese]

On Sunday 22 October 2006 04:38, Leonid wrote:
> [Leonid] Actually I could make spd_sdram work for my board (our HW guy
> hooked up DIMM EEPROM connections for me). I stepped through code using
> debugger and found out that EEPROM (address 0x51 on our board) has been
> successfully read, all parameters were sane and SDRAM registers have
> been updated accordantly.

OK. So far so good.

> However sdram0_mcsts register's most 
> significant bit never becomes 1, meaning SDRAM controller cannot
> complete memory initialization and code stays in endless loop:
>
> 	/*
> 	 * wait for SDRAM_CFG0_DC_EN to complete
> 	 */
> 	while (1) {
> 		mfsdram(mem_mcsts, mcsts);
> 		if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
> 			break;
> 		}
> 	}
>
> That looks like HW problem for me.

Yes. I never have seen a board where this did not happen. Did you try to skip 
this test to see, if the DDR interface perhaps works without this bit set? 
(Just a test of course, no solution).

I have to admit, that I don't know what problems would result in this bit not 
being set, apart from DC_EN not set in the SDRAM0_CFG0 register.

> Of course, I'll look through actual 
> registers' values more carefully - may be spd_sdram() just parsed EEPROM
> parameters wrongly but I doubt that.
>
> Just in case - did you happen to have BDI config file for that board -
> brief search in the ftp://ftp.denx.de/pub/BDI2000/ directory didn't
> provide results.

Yes. Please find it attached.

Best regards,
Stefan
-------------- next part --------------
;bdiGDB configuration file for IBM 440GX Reference Board
; ------------------------------------------------------
;
[INIT]
; Setup TLB
WTLB    0xF0000095  0x0F00003F  ;Boot Space 256MB
WTLB    0x00000094  0x0000003F  ;SDRAM 256MB @ 0x00000000
WTLB    0xd0000095  0x2000001B  ;PCI Page Entry
WTLB    0xe0000095  0x1400001B  ;Peripheral Page Entry
;
; Setup caches
WSPR    0x370   0x00000000      ;INV0
WSPR    0x371   0x00000000      ;INV1
WSPR    0x372   0x00000000      ;INV2
WSPR    0x373   0x00000000      ;INV3
WSPR    0x390   0x00000000      ;DNV0
WSPR    0x391   0x00000000      ;DNV1
WSPR    0x392   0x00000000      ;DNV2
WSPR    0x393   0x00000000      ;DNV3
WSPR    0x398   0x0001f800      ;DVLIM
WSPR    0x399   0x0001f800      ;IVLIM
;
; Setup Peripheral Bus
WDCR	0x12	0x00000010	;Select EBC0_B0AP
WDCR	0x13	0x04055200	;B0AP: Flash and SRAM
WDCR	0x12	0x00000000	;Select EBC0_B0CR
WDCR	0x13	0xfff18000	;B0CR: 1MB at 0xFFF00000, r/w, 8bit
;WDCR	0x12	0x00000012	;Select EBC0_B2AP
;WDCR	0x13	0x05055200	;B2AP: 4 MB Flash
;WDCR	0x12	0x00000002	;Select EBC0_B2CR
;WDCR	0x13	0xff838000	;B2CR: 2MB at 0xFFE00000, r/w, 8bit
;
; Setup SDRAM Controller (DDR SDRAM)
WDCR	0x10	0x00000082	;Select SDRAM0_CLKTR
WDCR	0x11	0x40000000	;CLKTR: Advance 90 degrees
WDCR	0x10	0x00000080	;Select SDRAM0_TR0
WDCR	0x11	0x410a4012	;TR0:
WDCR	0x10	0x00000081	;Select SDRAM0_TR1
WDCR	0x11	0x8080080b	;TR1:
WDCR	0x10	0x00000040	;Select SDRAM0_B0CR
WDCR	0x11	0x000a4001	;B0CR:
WDCR	0x10	0x00000044	;Select SDRAM0_B1CR
WDCR	0x11	0x080a4001	;B1CR:
WDCR	0x10	0x00000030	;Select SDRAM0_RTR
WDCR	0x11	0x04080000	;RTR:
WDCR	0x10	0x00000020	;Select SDRAM0_CFG0
WDCR	0x11	0x34000000	;CFG0: enable SDRAM
WDCR	0x11	0x84000000	;CFG0: enable SDRAM
DELAY   100
;
; Setup default vector table
WSPR    0x03f   0x00000000      ;IVPR   vector base at 0x00000000
WSPR    0x190   0x00000100      ;IVOR0  Critical Input
WSPR    0x191   0x00000200      ;IVOR1  Machine Check
WSPR    0x192   0x00000300      ;IVOR2  Data Storage
WSPR    0x193   0x00000400      ;IVOR3  Instruction Storage
WSPR    0x194   0x00000500      ;IVOR4  External Input
WSPR    0x195   0x00000600      ;IVOR5  Alignment
WSPR    0x196   0x00000700      ;IVOR6  Program
WSPR    0x197   0x00000800      ;IVOR7  Reserved
WSPR    0x198   0x00000c00      ;IVOR8  System Call
WSPR    0x199   0x00000a00      ;IVOR9  Reserved
WSPR    0x19a   0x00001000      ;IVOR10 Decrementer
WSPR    0x19b   0x00001010      ;IVOR11 Fixed Interval Timer
WSPR    0x19c   0x00001020      ;IVOR12 Watchdog Timer
WSPR    0x19d   0x00001100      ;IVOR13 Data TLB Error
WSPR    0x19e   0x00001200      ;IVOR14 Instruction TLB Error
WSPR    0x19f   0x00000f00      ;IVOR15 Debug
;
; Clear DBCR1 and DBCR2
WSPR    0x135   0x00000000      ;DBCR1
WSPR    0x136   0x00000000      ;DBCR2


[TARGET]
JTAGCLOCK   0                   ;use 16 MHz JTAG clock
CPUTYPE     440 		;the used target CPU type
SCANMISC    8                   ;IR length is 8 bits for 440GX
WAKEUP      50                  ;wakeup time after reset
;BREAKMODE   SOFT      	        ;SOFT or HARD, HARD uses PPC hardware breakpoint
BREAKMODE   HARD      	        ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    JTAG                ;JTAG or HWBP, HWBP uses one or two hardware breakpoints
;MMU         XLAT 0xC0000000     ;enable virtual address mode
;PTBASE      0x00000000          ;address where kernel/user stores pointer to page table
;SIO         7 9600              ;TCP port for serial IO
;REGLIST     ALL                 ;select register to transfer to GDB


[HOST]
IP          192.168.1.1
FILE        /tftpboot/yosemite/u-boot.bin
FORMAT      BIN
DUMP        /tftpboot/yosemite/dump.bin
PROMPT      440EP>


[FLASH]
; user flash at 0xff800000, AM29LV033C (4M x 8)
;WORKSPACE   0xFF800000  ;workspace in SRAM for fast programming algorithm
;WORKSPACE   0x00100000  ;workspace in SDRAM for fast programming algorithm
;CHIPTYPE    AM29BX16    ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPTYPE    AM29F    ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPSIZE    0x80000    ;The size of one flash chip in bytes
BUSWIDTH    8          ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        /tftpboot/pcs440ep/u-boot.bin
FORMAT      BIN 0xFFFA0000
;ERASE       0xFFF80000  ;erase sector
;ERASE       0xFFF90000  ;erase sector
ERASE       0xFFFA0000  ;erase sector
ERASE       0xFFFB0000  ;erase sector
ERASE       0xFFFC0000  ;erase sector
ERASE       0xFFFD0000  ;erase sector
ERASE       0xFFFE0000  ;erase sector
ERASE       0xFFFF0000  ;erase sector

[REGS]
IDCR1	0x010	0x011	;SDRAM0_CFGADDR and SDRAM0_CFGDATA
IDCR2	0x012	0x013	;EBC0_CFGADDR   and EBC0_CFGDATA
IDCR3	0x014	0x015	;EBM0_CFGADDR   and EBM0_CFGDATA
IDCR4	0x016	0x017	;PPM0_CFGADDR   and PPM0_CFGDATA
IDCR5	0x00C	0x00D	;CPR0_CFGADDR   and CPR0_CFGDATA
IDCR6	0x00E	0x00F	;SDR0_CFGADDR   and SDR0_CFGDATA
DMM1    0xD0000000      ;PCI        (should map to 2_000_0000)
DMM2    0xE0000000      ;Peripheral (should map to 1_400_0000)
FILE    /tftpboot/BDI2000/reg440gx.def

[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Leonid]

On Sunday, October 22, 2006 4:13 AM Stefan Roese wrote:
> > Actually I could make spd_sdram work for my board (our HW guy
> > hooked up DIMM EEPROM connections for me). I stepped through code
using
> > debugger and found out that EEPROM (address 0x51 on our board) has
been
> > successfully read, all parameters were sane and SDRAM registers have
> > been updated accordantly.

> OK. So far so good.

> > However sdram0_mcsts register's most 
> > significant bit never becomes 1, meaning SDRAM controller cannot
> > complete memory initialization and code stays in endless loop:
> > That looks like HW problem for me.

> Yes. I never have seen a board where this did not happen. Did you try
to 
> skip this test to see, if the DDR interface perhaps works without this
bit 
> set? (Just a test of course, no solution).

[Leonid] It was first thing I tried - just leave the loop after 1 mln
loops even if status is not ready. It fails on memory test in
program_tr1() function. I'll work with our HW folks to see what can be
done.

Best regards,
Leonid.

[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Leonid]

On Sunday, October 22, 2006 4:13 AM Stefan Roese wrote:
> > However sdram0_mcsts register's most 
> > significant bit never becomes 1, meaning SDRAM controller cannot
> > complete memory initialization and code stays in endless loop:
> > That looks like HW problem for me.

> Yes. I never have seen a board where this did not happen. 

Now I pass sdram0_mcsts status check (our HW folks said there was some
clock marginality they fixed) and proceed to program_tr1() function
which fails:

U-Boot 1.1.4 (Oct 23 2006 - 20:28:01)

CPU:   AMCC PowerPC 440EP Rev. B at 333.333 MHz (PLB=133, OPB=66, EBC=33
MHz)
       I2C boot EEPROM disabled
       Internal PCI arbiter disabled, PCI async ext clock used
       32 kB I-Cache 32 kB D-Cache
Board: Yosemite - AMCC PPC440EP Evaluation Board
I2C:   ready
DRAM:  get_spd_info banks 1 Addresses: 0x51
DIMM: slot 0: populated, bytes 128 size 8
DIMM: slot 0: DDR SDRAM detected
DIMM: 0 voltage level supported.
DIMM: sdram0_cfg0 0x02000000 -> 0x00000000 -> 0x04000000.
DIMM: sdram0_cfg1 0x00000000 -> 0x00000000.
DIMM: sdram0_rtr 0x04100000.
DIMM: sdram0_tr0 0x00894012 -> 0x00000000 -> 0x408A4012.
DIMM: sdram0_b0cr 0x000C6001 base 0x00000000 size 0x10000000.
DIMM: sdram0_b1cr 0x100C6001 base 0x10000000 size 0x10000000.
DIMM: total size 0x20000000
Starting memory test ....
ERROR: Cannot determine a common read delay.
### ERROR ### Please RESET the board ###

I tried several hardcoded tr1 values, it doesn't work either - code
crashes on read/write attempts - I must investigate where exactly by
reviewing assembler - GDB debugging on C level was not very helpful. But
I believe it still same HW problem - situation became better, yet not
good enough... 

Best regards,
Leonid.

[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Stefan Roese]

On Tuesday 24 October 2006 06:14, Leonid wrote:
> Now I pass sdram0_mcsts status check (our HW folks said there was some
> clock marginality they fixed

Hopefully no further "marginality" problems are hidden.

> ) and proceed to program_tr1() function 
> which fails:
>
> U-Boot 1.1.4 (Oct 23 2006 - 20:28:01)
>
> CPU:   AMCC PowerPC 440EP Rev. B at 333.333 MHz (PLB=133, OPB=66, EBC=33
> MHz)
>        I2C boot EEPROM disabled
>        Internal PCI arbiter disabled, PCI async ext clock used
>        32 kB I-Cache 32 kB D-Cache
> Board: Yosemite - AMCC PPC440EP Evaluation Board
> I2C:   ready
> DRAM:  get_spd_info banks 1 Addresses: 0x51
> DIMM: slot 0: populated, bytes 128 size 8
> DIMM: slot 0: DDR SDRAM detected
> DIMM: 0 voltage level supported.
> DIMM: sdram0_cfg0 0x02000000 -> 0x00000000 -> 0x04000000.
> DIMM: sdram0_cfg1 0x00000000 -> 0x00000000.
> DIMM: sdram0_rtr 0x04100000.
> DIMM: sdram0_tr0 0x00894012 -> 0x00000000 -> 0x408A4012.
> DIMM: sdram0_b0cr 0x000C6001 base 0x00000000 size 0x10000000.
> DIMM: sdram0_b1cr 0x100C6001 base 0x10000000 size 0x10000000.
> DIMM: total size 0x20000000
> Starting memory test ....
> ERROR: Cannot determine a common read delay.
> ### ERROR ### Please RESET the board ###
>
> I tried several hardcoded tr1 values, it doesn't work either - code
> crashes on read/write attempts - I must investigate where exactly by
> reviewing assembler - GDB debugging on C level was not very helpful. But
> I believe it still same HW problem - situation became better, yet not
> good enough...

Did you try different DDR modules? I would suggest to start with small 
modules, perhaps only with one bank. For bigger modules you have to make sure 
that enough TLB entries are set up.

Best regards,
Stefan