From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Fri, 11 May 2007 10:35:00 +0200 Subject: [U-Boot-Users] [PATCH] One more patch for the sequoia In-Reply-To: <1628E43D99629C46988BE46087A3FBB997B71C@ep-01.EmbeddedPlanet.local> References: <1628E43D99629C46988BE46087A3FBB997B71C@ep-01.EmbeddedPlanet.local> Message-ID: <200705111035.00728.sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Jeff, On Wednesday 09 May 2007, Jeff Mann wrote: > I've tried again. (attched this time so that OUTLOOK does not mess up > the formating.) > > Explanation of attached patch: > > Because the Sequoia board does not boot with an EBC faster than 66MHz, > the clock divider are changed after the initial boot process. > > This allows for maximum clocking speeds to be achieved on newer boards. > Sequoia boards with 666.66 MHz processors require that the EBC divider > be set to 3 in order to start the initial boot process at a slower EBC > speed. After the initial boot process, the divider can be set back to 2, > > which will cause the boards to run at 83.333MHz. This is backward > compatible with boards with 533.33 MHz processors, as these boards will > already be set with an EBC divider of 2. I made small cosmetic changes. Please give the attached version a try and let me know if it still works for you. Thanks. diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 930fa71..8704014 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -132,6 +132,12 @@ int board_early_init_f(void) (0x80000000 >> (28 + CFG_NAND_CS)); mtsdr(SDR0_CUST0, sdr0_cust0); + /* Update EBC speed after booting from i2c bootstrap settings + * on newer boards with 33.333 MHZ Clocks + */ + if (in8(CFG_BCSR_BASE + 3) & 0x80) + mtcpr(0xe0, 0x02000000); + return 0; } @@ -363,8 +369,8 @@ int checkboard(void) printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); #endif - rev = *(u8 *)(CFG_BCSR_BASE + 0); - val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01; + rev = in8(CFG_BCSR_BASE + 0); + val = in8(CFG_BCSR_BASE + 5) & 0x01; printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); if (s != NULL) { diff --git a/include/ppc440.h b/include/ppc440.h index bc1d7aa..07f75de 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1425,9 +1425,6 @@ /*----------------------------------------------------------------------------+ | Clock / Power-on-reset DCR's. +----------------------------------------------------------------------------*/ -#define CPR0_CFGADDR 0x00C -#define CPR0_CFGDATA 0x00D - #define CPR0_CLKUPD 0x20 #define CPR0_CLKUPD_BSY_MASK 0x80000000 #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 @@ -3314,6 +3311,23 @@ #define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) #define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) +/* + * All 44x except 440GP have CPR registers (indirect DCR) + */ +#if !defined(CONFIG_440GP) +#define CPR0_CFGADDR 0x00C +#define CPR0_CFGDATA 0x00D + +#define mtcpr(reg, data) do { \ + mtdcr(CPR0_CFGADDR, reg); \ + mtdcr(CPR0_CFGDATA, data); \ + } while (0) + +#define mfcpr(reg, data) do { \ + mtdcr(CPR0_CFGADDR, reg); \ + data = mfdcr(CPR0_CFGDATA); \ + } while (0) +#endif #ifndef __ASSEMBLY__