[U-Boot-Users] adding support to new board

[U-Boot-Users] adding support to new board

[Jeff Mann]

See http://www.freescale.com/files/32bit/doc/app_note/AN3220.pdf

-JM 

-----Original Message-----
From: u-boot-users-bounces@lists.sourceforge.net
[mailto:u-boot-users-bounces at lists.sourceforge.net] On Behalf Of Maximus
Sent: Saturday, July 15, 2006 5:31 AM
To: U-Boot-Users at lists.sourceforge.net
Subject: [U-Boot-Users] adding support to new board

Hi,
  Is there any document (step by step) approach on how to add u-boot
support to a new board?

  any advices,


Regards,
jo


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[U-Boot-Users] adding support to new board

[Wolfgang Denk]

In message <1628E43D99629C46988BE46087A3FBB9607B79@ep-01.EmbeddedPlanet.local> you wrote:
> See http://www.freescale.com/files/32bit/doc/app_note/AN3220.pdf

Ummm... don't, please.

This document is not really helpful.  It  explains  a  few  bits  and
pieces  which apply to MPC5200 systems only, and fails to explain any
context or relations between config options and code.

IMHO it does more harm then help.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Just about every computer on the market today runs Unix,  except  the
Mac (and nobody cares about it).                   - Bill Joy 6/21/85

[U-Boot-Users] DDR2 (Moduel 512M) work unstablely when enable the ECC

[jxnuxdy]

Hi,     I bring up the u-boot in my 440EPx based on board successfully, it work fine when I disable the ECC, however when I enable the ECC I found it work unstablely in u-boot, for example it sometimes crashed in 'tftp' download.     Is there someone also encounter this issue? My code AS below:long int sequoia_sdram_init (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 u32 val = 0;
 ulong speed = get_bus_freq(0); mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A);
 mtsdram(DDR0_01, 0x01000000);
 mtsdram(DDR0_03, 0x02030602); //CASLAT = 3, CLATLN = 3
 //mtsdram(DDR0_03, 0x02040802); //CASLAT = 4, CLATLN = 4 //mtsdram(DDR0_04, 0x0A020200);
 mtsdram(DDR0_04, 0x0C020200); mtsdram(DDR0_05, 0x02020308);
 mtsdram(DDR0_06, 0x0102C812);
 mtsdram(DDR0_07, 0x000D0100);
 // mtsdram(DDR0_08, 0x02430001); //WR = 2 (far CAS 3)
 mtsdram(DDR0_08, 0x02C80001); //when in doubt set tcpd to 200cycles 08/28/07
 //mtsdram(DDR0_08, 0x03430001); //WR = 2 (far CAS 4) //mtsdram(DDR0_09, 0x00011D5F); // 75ohm RTT //mtsdram(DDR0_09, 0x00001D5F); // Termination disabled /* for tuning WDS */
 //mtsdram(DDR0_09, 0x00011D50);
 //mtsdram(DDR0_09, 0x00011D4F);
 mtsdram(DDR0_09, 0x00011D40); //mtsdram(DDR0_10, 0x00000300); // dual rank mtsdram(DDR0_10, 0x00000100); // single rank mtsdram(DDR0_11, 0x0027C800);
 mtsdram(DDR0_12, 0x00000003);
 //mtsdram(DDR0_14, 0x00000000);
 mtsdram(DDR0_14, 0x00000100);
 mtsdram(DDR0_17, 0x19000000);
 mtsdram(DDR0_18, 0x19191919);
 mtsdram(DDR0_19, 0x19191919);
 mtsdram(DDR0_20, 0x0B0B0B0B);
 mtsdram(DDR0_21, 0x0B0B0B0B);
 //mtsdram(DDR0_22, 0x00267F0B); // no ECC
 //mtsdram(DDR0_22, 0x03267F0B); // enable ECC /* for tuning DQSOSH */
 //mtsdram(DDR0_22, 0x0026700B); // no ECC
 //mtsdram(DDR0_22, 0x03266F0B); // ECC
 mtsdram(DDR0_22, 0x0026600B); // ECC mtsdram(DDR0_23, 0x00000000);
 //mtsdram(DDR0_24, 0x01010002); //ODT_WR_MAP_CS0 =
 mtsdram(DDR0_24, 0x01010001); //ODT_WR_MAP_CS0 = printf("DDR Init: speed = %d \n", speed);
 if (speed > 133333334) {
  mtsdram(DDR0_26, 0x5B26050C);
 }
 else {
  mtsdram(DDR0_26, 0x5B260408);
 } mtsdram(DDR0_27, 0x0000682B);
 mtsdram(DDR0_28, 0x00000000);
 mtsdram(DDR0_31, 0x00000000);
 //mtsdram(DDR0_42, 0x01000006);
 mtsdram(DDR0_42, 0x00000006);
 mtsdram(DDR0_43, 0x030A0200);
 mtsdram(DDR0_44, 0x00000003);
 mtsdram(DDR0_02, 0x00000001); wait_for_dlllock();
#endif /* #ifndef CONFIG_NAND_U_BOOT */#ifdef CONFIG_DDR_DATA_EYE
 /* -----------------------------------------------------------+
  * Perform data eye search if requested.
  * ----------------------------------------------------------*/
 denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
#endif#ifdef CONFIG_DDR_ECC{
 unsigned long write_addr;
 unsigned long registerVal;
 unsigned long memory_size = (CFG_MBYTES_SDRAM << 20); /* 0- Enable ECC */
 mtdcr(ddrcfga, DDR0_22);
 registerVal = mfdcr(ddrcfgd);
 registerVal = (registerVal &~ DDR0_22_CTRL_RAW_MASK) | DDR0_22_CTRL_RAW_ECC_ENABLE;
 mtdcr(ddrcfgd, registerVal); /* 1- Clear entire memory content */
 write_addr = CFG_SDRAM_BASE;
 printf("ECC Enabling\n");
 printf("Start memory clearing @ 0x%08x size = 0x%08x...", write_addr, memory_size);
 while (write_addr < memory_size) {
  *((unsigned long*)write_addr) = write_addr;
  write_addr += 8;
#ifdef DDR_DEBUG_SIZE
  if ( (write_addr % 0x10000000 ) == 0)
   printf("addr = 0x%08x \n", write_addr );
#endif
 }
 printf("   DONE\n"); /* 2- Clear error status */
 mtdcr(ddrcfga, DDR0_00);
 registerVal = mfdcr(ddrcfgd);
 mtdcr(ddrcfgd, (registerVal | DDR0_00_INT_ACK_ALL)); /* 3- Set 'int_mask' parameter to functionnal value */
 #ifdef DDR_DEBUG
 printf("Set 'int_mask' parameter to functionnal value\n");
 #endif
 mtdcr(ddrcfga, DDR0_01);
 registerVal = mfdcr(ddrcfgd); mtdcr(ddrcfgd, ((registerVal &~ DDR0_01_INT_MASK_MASK)
  | DDR0_01_INT_MASK_ALL_OFF));
}
#endif mtdcr(ddrcfga, DDR0_02);
 val = mfdcr(ddrcfgd); //dump_ddr2_regs(); return (CFG_MBYTES_SDRAM << 20);
}  - Denny 
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[U-Boot-Users] DDR2 (Moduel 512M) work unstablely when enable the ECC

[Stefan Roese]

Hi Denny,

On Wednesday 26 September 2007, jxnuxdy wrote:
> Hi,     I bring up the u-boot in my 440EPx based on board successfully, it
> work fine when I disable the ECC, however when I enable the ECC I found it
> work unstablely in u-boot, for example it sometimes crashed in 'tftp'
> download.     Is there someone also encounter this issue?

Yes, we have a custom board that possibly has some problems with ECC on 440EPx 
too.

Could you please send your code in a more readable form? And is your board 
able to boot an OS (Linux etc.) without ECC enabled? Did you run some memory 
tests?

Best regards,
Stefan

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