From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Fri, 4 Jan 2008 07:37:19 +0100 Subject: [U-Boot-Users] [PATCH (RESUBMIT)] ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia board In-Reply-To: <477D76C1.4070509@acm.org> References: <477D76C1.4070509@acm.org> Message-ID: <200801040737.19671.sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Larry, On Friday 04 January 2008, Lawrence R. Johnson wrote: > Note: this patch changes the configuration of some GPIO registers: > > Register Old Value New Value > --------------- ---------- ---------- > DCR GPIO0_TCR 0x0000000F 0x0000F0CF > DCR GPIO0_TSRH 0x55005000 0x00000000 > DCR GPIO1_TCR 0xC2000000 0xE2000000 > DCR GPIO1_TSRL 0x0C000000 0x00200000 > DCR GPIO1_ISR2L 0x00050000 0x00110000 > > Signed-off-by: Larry Johnson > --- > Hi Stefan, > > This is my attempt to use apply the new GPIO configuration to the > Sequoia board. I didn't find much about GPIO in the Sequoia manual, so > I just tried to produce a table that matched the current Sequoia > configuration as closely as possible. > > I think the changed values above are OK. The TCR and TSR changes are > generated from the table, and should be correct. The ISR change > reflects that GPIO37 Alt2 is bidirectional, and GPIO38 Alt2 is an > output. Thanks a lot for the good work. Really appreciated. I'll re-check the Sequouia values again. Please find one further comment below. > Best regards, > Larry > > N.B.: This patch depends on my previously-submitted patch for GPIO. > > board/amcc/sequoia/sequoia.c | 31 +------------ > include/configs/sequoia.h | 106 > ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 107 > insertions(+), 30 deletions(-) > > diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c > index 37b4f31..2268bc0 100644 > --- a/board/amcc/sequoia/sequoia.c > +++ b/board/amcc/sequoia/sequoia.c > @@ -26,6 +26,7 @@ > #include > #include > #include > +#include > #include > #include > > @@ -45,36 +46,6 @@ int board_early_init_f(void) > mtdcr(ebccfgd, 0xb8400000); > > /*-------------------------------------------------------------------- > - * Setup the GPIO pins > - *-------------------------------------------------------------------*/ > - /* test-only: take GPIO init from pcs440ep ???? in config file */ > - out_be32((u32 *) GPIO0_OR, 0x00000000); > - out_be32((u32 *) GPIO0_TCR, 0x0000000f); > - out_be32((u32 *) GPIO0_OSRL, 0x50015400); > - out_be32((u32 *) GPIO0_OSRH, 0x550050aa); > - out_be32((u32 *) GPIO0_TSRL, 0x50015400); > - out_be32((u32 *) GPIO0_TSRH, 0x55005000); > - out_be32((u32 *) GPIO0_ISR1L, 0x50000000); > - out_be32((u32 *) GPIO0_ISR1H, 0x00000000); > - out_be32((u32 *) GPIO0_ISR2L, 0x00000000); > - out_be32((u32 *) GPIO0_ISR2H, 0x00000100); > - out_be32((u32 *) GPIO0_ISR3L, 0x00000000); > - out_be32((u32 *) GPIO0_ISR3H, 0x00000000); > - > - out_be32((u32 *) GPIO1_OR, 0x00000000); > - out_be32((u32 *) GPIO1_TCR, 0xc2000000); > - out_be32((u32 *) GPIO1_OSRL, 0x5c280000); > - out_be32((u32 *) GPIO1_OSRH, 0x00000000); > - out_be32((u32 *) GPIO1_TSRL, 0x0c000000); > - out_be32((u32 *) GPIO1_TSRH, 0x00000000); > - out_be32((u32 *) GPIO1_ISR1L, 0x00005550); > - out_be32((u32 *) GPIO1_ISR1H, 0x00000000); > - out_be32((u32 *) GPIO1_ISR2L, 0x00050000); > - out_be32((u32 *) GPIO1_ISR2H, 0x00000000); > - out_be32((u32 *) GPIO1_ISR3L, 0x01400000); > - out_be32((u32 *) GPIO1_ISR3H, 0x00000000); > - > - /*-------------------------------------------------------------------- > * Setup the interrupt controller polarities, triggers, etc. > *-------------------------------------------------------------------*/ > mtdcr(uic0sr, 0xffffffff); /* clear all */ > diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h > index 1f72b54..86dd9d6 100644 > --- a/include/configs/sequoia.h > +++ b/include/configs/sequoia.h > @@ -476,6 +476,112 @@ > #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) > #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ > > +/*----------------------------------------------------------------------- > + * PPC440 GPIO Configuration > + */ > +/* test-only: take GPIO init from pcs440ep ???? in config file */ > +/* > + TEST_DCR(GPIO0_OR, 0x00000000); > + TEST_DCR(GPIO0_TCR, 0x0000000f); > + TEST_DCR(GPIO0_OSRL, 0x50015400); > + TEST_DCR(GPIO0_OSRH, 0x550050aa); > + TEST_DCR(GPIO0_TSRL, 0x50015400); > + TEST_DCR(GPIO0_TSRH, 0x55005000); > + TEST_DCR(GPIO0_ISR1L, 0x50000000); > + TEST_DCR(GPIO0_ISR1H, 0x00000000); > + TEST_DCR(GPIO0_ISR2L, 0x00000000); > + TEST_DCR(GPIO0_ISR2H, 0x00000100); > + TEST_DCR(GPIO0_ISR3L, 0x00000000); > + TEST_DCR(GPIO0_ISR3H, 0x00000000); > + > + > + TEST_DCR(GPIO1_OR, 0x00000000); > + TEST_DCR(GPIO1_TCR, 0xc2000000); > + TEST_DCR(GPIO1_OSRL, 0x5c280000); > + TEST_DCR(GPIO1_OSRH, 0x00000000); > + TEST_DCR(GPIO1_TSRL, 0x0c000000); > + TEST_DCR(GPIO1_TSRH, 0x00000000); > + TEST_DCR(GPIO1_ISR1L, 0x00005550); > + TEST_DCR(GPIO1_ISR1H, 0x00000000); > + TEST_DCR(GPIO1_ISR2L, 0x00050000); > + TEST_DCR(GPIO1_ISR2H, 0x00000000); > + TEST_DCR(GPIO1_ISR3L, 0x01400000); > + TEST_DCR(GPIO1_ISR3H, 0x00000000); > +*/ What are these TEST_DCR()'s for? Please remove and resumbit. Thanks. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================