* [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile.
@ 2008-01-11 0:12 Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1 Heiko Schocher
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Heiko Schocher @ 2008-01-11 0:12 UTC (permalink / raw)
To: u-boot
Signed-off-by: Heiko Schocher <hs@denx.de>
---
MAKEALL | 1 +
Makefile | 3 +
board/mgsuvd/Makefile | 44 ++++++
board/mgsuvd/config.mk | 28 ++++
board/mgsuvd/mgsuvd.c | 216 ++++++++++++++++++++++++++++++
board/mgsuvd/u-boot.lds | 144 ++++++++++++++++++++
cpu/mpc8xx/cpu.c | 16 +++
include/commproc.h | 26 ++++
include/configs/mgsuvd.h | 325 ++++++++++++++++++++++++++++++++++++++++++++++
9 files changed, 803 insertions(+), 0 deletions(-)
create mode 100644 board/mgsuvd/Makefile
create mode 100644 board/mgsuvd/config.mk
create mode 100644 board/mgsuvd/mgsuvd.c
create mode 100644 board/mgsuvd/u-boot.lds
create mode 100644 include/configs/mgsuvd.h
diff --git a/MAKEALL b/MAKEALL
index 4cbddc2..3224497 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -107,6 +107,7 @@ LIST_8xx=" \
lwmon \
MBX \
MBX860T \
+ mgsuvd \
MHPC \
MPC86xADS \
MPC885ADS \
diff --git a/Makefile b/Makefile
index 35e9031..7c1fbb8 100644
--- a/Makefile
+++ b/Makefile
@@ -846,6 +846,9 @@ MBX_config \
MBX860T_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx
+mgsuvd_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd
+
MHPC_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
diff --git a/board/mgsuvd/Makefile b/board/mgsuvd/Makefile
new file mode 100644
index 0000000..af0d400
--- /dev/null
+++ b/board/mgsuvd/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2007
+# Heiko Schocher, DENX Software Engineering, hs at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mgsuvd/config.mk b/board/mgsuvd/config.mk
new file mode 100644
index 0000000..8625cea
--- /dev/null
+++ b/board/mgsuvd/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2007
+# Heiko Schocher, DENX Software Engineering, hs at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mgsvud boards
+#
+
+TEXT_BASE = 0xf0000000
diff --git a/board/mgsuvd/mgsuvd.c b/board/mgsuvd/mgsuvd.c
new file mode 100644
index 0000000..dd7d823
--- /dev/null
+++ b/board/mgsuvd/mgsuvd.c
@@ -0,0 +1,216 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const uint sdram_table[] =
+{
+ 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
+ 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ /* 0x08 Burst Read */
+ 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
+ 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
+ /* 0x10 Load mode register */
+ 0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ /* 0x18 Single Write */
+ 0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
+ 0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
+ /* 0x20 Burst Write */
+ 0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
+ 0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
+ 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ /* 0x30 Precharge all and Refresh */
+ 0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
+ 0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ /* 0x3C Exception */
+ 0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+};
+
+int checkboard (void)
+{
+ puts ("Board: Keymile mgsuvd\n");
+ return (0);
+}
+
+long int initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size;
+
+ upmconfig (UPMB, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
+
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR;
+
+ /*
+ * The following value is used as an address (i.e. opcode) for
+ * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+ * the port size is 32bit the SDRAM does NOT "see" the lower two
+ * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+ * MICRON SDRAMs:
+ * -> 0 00 010 0 010
+ * | | | | +- Burst Length = 4
+ * | | | +----- Burst Type = Sequential
+ * | | +------- CAS Latency = 2
+ * | +----------- Operating Mode = Standard
+ * +-------------- Write Burst Mode = Programmed Burst Length
+ */
+ memctl->memc_mar = CFG_MAR;
+
+ /*
+ * Map controller banks 1 to the SDRAM banks 1 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
+
+ memctl->memc_mbmr = CFG_MBMR & (~(MBMR_PTBE)); /* no refresh yet */
+
+ udelay (200);
+
+ /* perform SDRAM initializsation sequence */
+
+ memctl->memc_mcr = 0x80802830; /* SDRAM bank 0 */
+ udelay (1);
+ memctl->memc_mcr = 0x80802110; /* SDRAM bank 0 - execute twice */
+ udelay (1);
+
+ memctl->memc_mbmr |= MBMR_PTBE; /* enable refresh */
+
+ udelay (1000);
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ */
+ size = get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
+ udelay (1000);
+
+ debug ("SDRAM Bank 0: %ld MB\n", size >> 20);
+
+ return (size);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+/*
+ * update "memory" property in the blob
+ */
+void ft_blob_update(void *blob, bd_t *bd)
+{
+ int ret, nodeoffset = 0;
+ ulong brg_data[1] = {0};
+ ulong memory_data[2] = {0};
+ ulong flash_data[4] = {0};
+
+ memory_data[0] = cpu_to_be32(bd->bi_memstart);
+ memory_data[1] = cpu_to_be32(bd->bi_memsize);
+
+ nodeoffset = fdt_path_offset (blob, "/memory");
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
+ sizeof(memory_data));
+ if (ret < 0)
+ printf("ft_blob_update): cannot set /memory/reg "
+ "property err:%s\n", fdt_strerror(ret));
+ }
+ else {
+ /* memory node is required in dts */
+ printf("ft_blob_update(): cannot find /memory node "
+ "err:%s\n", fdt_strerror(nodeoffset));
+ }
+
+ flash_data[2] = cpu_to_be32(bd->bi_flashstart);
+ flash_data[3] = cpu_to_be32(bd->bi_flashsize);
+ nodeoffset = fdt_path_offset (blob, "/localbus");
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data,
+ sizeof(flash_data));
+ if (ret < 0)
+ printf("ft_blob_update): cannot set /localbus/ranges "
+ "property err:%s\n", fdt_strerror(ret));
+ }
+ else {
+ /* memory node is required in dts */
+ printf("ft_blob_update(): cannot find /localbus node "
+ "err:%s\n", fdt_strerror(nodeoffset));
+ }
+ /* BRG */
+ brg_data[0] = cpu_to_be32(bd->bi_busfreq);
+ nodeoffset = fdt_path_offset (blob, "/soc866/cpm");
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data,
+ sizeof(brg_data));
+ if (ret < 0)
+ printf("ft_blob_update): cannot set /soc866/cpm/brg-frequency "
+ "property err:%s\n", fdt_strerror(ret));
+ }
+ else {
+ /* memory node is required in dts */
+ printf("ft_blob_update(): cannot find /localbus node "
+ "err:%s\n", fdt_strerror(nodeoffset));
+ }
+ /* MAC Adresse */
+ nodeoffset = fdt_path_offset (blob, "/soc866/cpm/scc");
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr,
+ sizeof(uchar) * 6);
+ if (ret < 0)
+ printf("ft_blob_update): cannot set /soc866/cpm/scc/mac-address "
+ "property err:%s\n", fdt_strerror(ret));
+ }
+ else {
+ /* memory node is required in dts */
+ printf("ft_blob_update(): cannot find /localbus node "
+ "err:%s\n", fdt_strerror(nodeoffset));
+ }
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup( blob, bd);
+ ft_blob_update(blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/mgsuvd/u-boot.lds b/board/mgsuvd/u-boot.lds
new file mode 100644
index 0000000..d526d1d
--- /dev/null
+++ b/board/mgsuvd/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ cpu/mpc8xx/traps.o (.text)
+ common/dlmalloc.o (.text)
+ lib_ppc/ppcstring.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+ lib_ppc/cache.o (.text)
+ lib_ppc/time.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.ppcenv)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c
index 97112f0..c878352 100644
--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@@ -39,6 +39,12 @@
#include <mpc8xx.h>
#include <asm/cache.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
static char *cpu_warning = "\n " \
@@ -632,3 +638,13 @@ void reset_8xx_watchdog (volatile immap_t * immr)
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_OF_LIBFDT)
+void ft_cpu_setup (void *blob, bd_t *bd)
+{
+ char * cpu_path = "/cpus/" OF_CPU;
+
+ do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
+ do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
+}
+#endif /* CONFIG_OF_LIBFDT */
diff --git a/include/commproc.h b/include/commproc.h
index 12400e3..53659c2 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -1120,6 +1120,32 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x0000003d)
#endif /* CONFIG_MBX */
+/*** MGSUVD *********************************************************/
+
+/* The MGSUVD Service Module uses SCC3 for Ethernet */
+
+#ifdef CONFIG_MGSUVD
+#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
+#define CPM_CR_ENET CPM_CR_CH_SCC3
+#define SCC_ENET 2
+#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */
+#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */
+#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */
+#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */
+
+#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
+
+#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */
+#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */
+
+/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
+ * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
+ */
+#define SICR_ENET_MASK ((uint)0x00FF0000)
+#define SICR_ENET_CLKRT ((uint)0x00250000)
+#endif /* CONFIG_MGSUVD */
+
+
/*** MHPC ********************************************************/
#if defined(CONFIG_MHPC)
diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h
new file mode 100644
index 0000000..13e7a7c
--- /dev/null
+++ b/include/configs/mgsuvd.h
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
+#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
+
+#define CONFIG_8xx_GCLK_FREQ 66000000
+
+#define CFG_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
+#define CFG_SMC_DPMEM_OFFSET 0x1fc0
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "addcon=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
+ "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcon;"\
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/mgsuvd/uImage\0" \
+ "fdt_addr=400000\0" \
+ "kernel_addr=200000\0" \
+ "fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=protect off f0000000 +${filesize};" \
+ "erase f0000000 +${filesize};" \
+ "cp.b 200000 f0000000 ${filesize};" \
+ "protect on f0000000 +${filesize}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
+
+#define CONFIG_TIMESTAMP /* but print image timestmps */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xf0000000
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_FLASH_SIZE 32
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#define CFG_SYPCR 0xffffff89
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR 0x00610480
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK 0x01800000
+#define CFG_SCCR 0x01800000
+
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+/*
+ * FLASH timing: Default value of OR0 after reset
+ */
+#define CFG_OR0_PRELIM 0xfe000954
+#define CFG_BR0_PRELIM 0xf0000401
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CFG_OR_TIMING_SDRAM 0x00000A00
+
+#define CFG_OR1_PRELIM 0xfc000800
+#define CFG_BR1_PRELIM (0x000000C0 | 0x01)
+
+#define CFG_MPTPR 0x0200
+/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
+ 1 Write loop Cycle (not used), 1 Timer Loop Cycle */
+#define CFG_MBMR 0x10964111
+#define CFG_MAR 0x00000088
+
+/*
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
+/* HS HS noch zu setzen */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CONFIG_SCC3_ENET
+#define CONFIG_ETHPRIME "SCC ETHERNET"
+#define CONFIG_HAS_ETH0
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,866 at 0"
+#define OF_SOC "soc at f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc/cpm/serial at a80"
+
+#endif /* __CONFIG_H */
--
1.5.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1.
2008-01-11 0:12 [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile Heiko Schocher
@ 2008-01-11 0:12 ` Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile Heiko Schocher
2008-01-11 23:35 ` [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1 Wolfgang Denk
2008-01-11 6:34 ` [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile Stefan Roese
2008-01-11 23:35 ` Wolfgang Denk
2 siblings, 2 replies; 14+ messages in thread
From: Heiko Schocher @ 2008-01-11 0:12 UTC (permalink / raw)
To: u-boot
Signed-off-by: Heiko Schocher <hs@denx.de>
---
README | 4 ++
cpu/mpc8xx/cpu_init.c | 6 ++-
cpu/mpc8xx/serial.c | 21 +++++++++++
cpu/mpc8xx/upatch.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++-
include/commproc.h | 2 +
5 files changed, 124 insertions(+), 3 deletions(-)
diff --git a/README b/README
index 26f93c2..f8a4f48 100644
--- a/README
+++ b/README
@@ -2269,6 +2269,10 @@ Low Level (hardware related) configuration options:
enable I2C microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [DSP2]
+- CFG_SMC_UCODE_PATCH, CFG_SMC_DPMEM_OFFSET [0x1FC0]:
+ enable SMC microcode relocation patch (MPC8xx);
+ define relocation offset in DPRAM [SMC1]
+
- CFG_SPI_UCODE_PATCH, CFG_SPI_DPMEM_OFFSET [0x1FC0]:
enable SPI microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [SCC4]
diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index c79e578..fb3414a 100644
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -31,7 +31,8 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
+#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
+ defined(CFG_SMC_UCODE_PATCH)
void cpm_load_patch (volatile immap_t * immr);
#endif
@@ -253,7 +254,8 @@ void cpu_init_f (volatile immap_t * immr)
immr->im_cpm.cp_rccr = CFG_RCCR;
#endif
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
+#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
+ defined(CFG_SMC_UCODE_PATCH)
cpm_load_patch (immr); /* load mpc8xx microcode patch */
#endif
}
diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index 68804cc..ad02299 100644
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -124,6 +124,12 @@ static int smc_init (void)
sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
+#ifdef CFG_SMC_UCODE_PATCH
+ up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
+#else
+ /* Disable relocation */
+ up->smc_rpbase = 0;
+#endif
/* Disable transmitter/receiver.
*/
@@ -212,6 +218,12 @@ static int smc_init (void)
up->smc_tbase = dpaddr+sizeof(cbd_t);
up->smc_rfcr = SMC_EB;
up->smc_tfcr = SMC_EB;
+#if defined (CFG_SMC_UCODE_PATCH)
+ up->smc_rbptr = up->smc_rbase;
+ up->smc_tbptr = up->smc_tbase;
+ up->smc_rstate = 0;
+ up->smc_tstate = 0;
+#endif
#if defined(CONFIG_MBX)
board_serial_init();
@@ -288,6 +300,9 @@ smc_putc(const char c)
smc_putc ('\r');
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+#ifdef CFG_SMC_UCODE_PATCH
+ up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
+#endif
tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
@@ -326,6 +341,9 @@ smc_getc(void)
unsigned char c;
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+#ifdef CFG_SMC_UCODE_PATCH
+ up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
+#endif
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
@@ -351,6 +369,9 @@ smc_tstc(void)
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+#ifdef CFG_SMC_UCODE_PATCH
+ up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
+#endif
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
diff --git a/cpu/mpc8xx/upatch.c b/cpu/mpc8xx/upatch.c
index eccff64..4d6c522 100644
--- a/cpu/mpc8xx/upatch.c
+++ b/cpu/mpc8xx/upatch.c
@@ -1,7 +1,8 @@
#include <common.h>
#include <commproc.h>
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
+#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
+ defined(CFG_SMC_UCODE_PATCH)
static void UcodeCopy (volatile cpm8xx_t *cpm);
@@ -32,13 +33,29 @@ void cpm_load_patch (volatile immap_t *immr)
}
#endif
+#ifdef CFG_SMC_UCODE_PATCH
+ {
+ volatile smc_uart_t *up = (smc_uart_t *) & immr->im_cpm.cp_dparam[PROFF_SMC1];
+ /* Activate the microcode per the instructions in the microcode manual */
+ /* NOTE: We're only relocating the SMC parameters. */
+ immr->im_cpm.cp_cpmcr1 = 0x8080; /* Write Trap register 1 value */
+ immr->im_cpm.cp_cpmcr2 = 0x8088; /* Write Trap register 2 value */
+ up->smc_rpbase = CFG_SMC_DPMEM_OFFSET; /* Where to relocte SMC params */
+ }
+#endif
+
/*
* Enable DPRAM microcode to execute from the first 512 bytes
* and a 256 byte extension of DPRAM.
*/
+#ifdef CFG_SMC_UCODE_PATCH
+ immr->im_cpm.cp_rccr |= 0x0002;
+#else
immr->im_cpm.cp_rccr |= 0x0001;
+#endif
}
+#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCh)
static ulong patch_2000[] = {
0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000,
0x5FEFADF7, 0x5F88ADF7, 0x5FEFAFF7, 0x5F88AFF7,
@@ -82,6 +99,81 @@ static ulong patch_2F00[] = {
0x35931497, 0x35376956, 0xBD697B9D, 0x96931313,
0x19797937, 0x69350000,
};
+#else
+
+static ulong patch_2000[] = {
+ 0x3fff0000, 0x3ffd0000, 0x3ffb0000, 0x3ff90000,
+ 0x5fefeff8, 0x5f91eff8, 0x3ff30000, 0x3ff10000,
+ 0x3a11e710, 0xedf0ccb9, 0xf318ed66, 0x7f0e5fe2,
+ 0x7fedbb38, 0x3afe7468, 0x7fedf4d8, 0x8ffbb92d,
+ 0xb83b77fd, 0xb0bb5eb9, 0xdfda7fed, 0x90bde74d,
+ 0x6f0dcbd3, 0xe7decfed, 0xcb50cfed, 0xcfeddf6d,
+ 0x914d4f74, 0x5eaedfcb, 0x9ee0e7df, 0xefbb6ffb,
+ 0xe7ef7f0e, 0x9ee57fed, 0xebb7effa, 0xeb30affb,
+ 0x7fea90b3, 0x7e0cf09f, 0xbffff318, 0x5fffdfff,
+ 0xac35efea, 0x7fce1fc1, 0xe2ff5fbd, 0xaffbe2ff,
+ 0x5fbfaffb, 0xf9a87d0f, 0xaef8770f, 0x7d0fb0a2,
+ 0xeffbbfff, 0xcfef5fba, 0x7d0fbfff, 0x5fba4cf8,
+ 0x7fddd09b, 0x49f847fd, 0x7efdf097, 0x7fedfffd,
+ 0x7dfdf093, 0xef7e7e1e, 0x5fba7f0e, 0x3a11e710,
+ 0xedf0cc87, 0xfb18ad0a, 0x1f85bbb8, 0x74283b7e,
+ 0x7375e4bb, 0x2ab64fb8, 0x5c7de4bb, 0x32fdffbf,
+ 0x5f0843f8, 0x7ce3e1bb, 0xe74f7ded, 0x6f0f4fe8,
+ 0xc7ba32be, 0x73f2efeb, 0x600b4f78, 0xe5bb760b,
+ 0x5388aef8, 0x4ef80b6a, 0xcfef9ee5, 0xabf8751f,
+ 0xefef5b88, 0x741f4fe8, 0x751e760d, 0x7fdb70dd,
+ 0x741cafce, 0xefcc7fce, 0x751e7088, 0x741ce7bb,
+ 0x334ecfed, 0xafdbefeb, 0xe5bb760b, 0x53ceaef8,
+ 0xafe8e7eb, 0x4bf8771e, 0x7e007fed, 0x4fcbe2cc,
+ 0x7fbc3085, 0x7b0f7a0f, 0x34b177fd, 0xb0e75e93,
+ 0xdf313e3b, 0xaf78741f, 0x741f30cc, 0xcfef5f08,
+ 0x741f3e88, 0xafb8771e, 0x5f437fed, 0x0bafe2cc,
+ 0x741ccfec, 0xe5ca53a9, 0x6fcb4f74, 0x5e89df27,
+ 0x2a923d14, 0x4b8fdf0c, 0x751f741c, 0x6c1eeffa,
+ 0xefea7fce, 0x6ffc309a, 0xefec3fca, 0x308fdf0a,
+ 0xadf85e7a, 0xaf7daefd, 0x5e7adf0a, 0x5e7aafdd,
+ 0x761f1088, 0x1e7c7efd, 0x3089fffe, 0x4908fb18,
+ 0x5fffdfff, 0xafbbf0f7, 0x4ef85f43, 0xadf81489,
+ 0x7a0f7089, 0xcfef5089, 0x7a0fdf0c, 0x5e7cafed,
+ 0xbc6e780f, 0xefef780f, 0xefef790f, 0xa7f85eeb,
+ 0xffef790f, 0xefef790f, 0x1489df0a, 0x5e7aadfd,
+ 0x5f09fffb, 0xe79aded9, 0xeff96079, 0x607ae79a,
+ 0xded8eff9, 0x60795edb, 0x607acfef, 0xefefefdf,
+ 0xefbfef7f, 0xeeffedff, 0xebffe7ff, 0xafefafdf,
+ 0xafbfaf7f, 0xaeffadff, 0xabffa7ff, 0x6fef6fdf,
+ 0x6fbf6f7f, 0x6eff6dff, 0x6bff67ff, 0x2fef2fdf,
+ 0x2fbf2f7f, 0x2eff2dff, 0x2bff27ff, 0x4e08fd1f,
+ 0xe5ff6e0f, 0xaff87eef, 0x7e0ffdef, 0xf11f6079,
+ 0xabf8f51e, 0x7e0af11c, 0x37cfae16, 0x7fec909a,
+ 0xadf8efdc, 0xcfeae52f, 0x7d0fe12b, 0xf11c6079,
+ 0x7e0a4df8, 0xcfea5ea0, 0x7d0befec, 0xcfea5ea2,
+ 0xe522efdc, 0x5ea2cfda, 0x4e08fd1f, 0x6e0faff8,
+ 0x7c1f761f, 0xfdeff91f, 0x6079abf8, 0x761cee00,
+ 0xf91f2bfb, 0xefefcfec, 0xf91f6079, 0x761c27fb,
+ 0xefdf5e83, 0xcfdc7fdd, 0x50f84bf8, 0x47fd7c1f,
+ 0x761ccfcf, 0x7eef7fed, 0x7dfd70ef, 0xef7e7f1e,
+ 0x771efb18, 0x6079e722, 0xe6bbe5bb, 0x2e66e5bb,
+ 0x600b2ee1, 0xe2bbe2bb, 0xe2bbe2bb, 0x2f5ee2bb,
+ 0xe2bb2ff9, 0x6079e2bb,
+};
+
+static ulong patch_2F00[] = {
+ 0x30303030, 0x3e3e3030, 0xaf79b9b3, 0xbaa3b979,
+ 0x9693369f, 0x79f79777, 0x97333fff, 0xfb3b9e9f,
+ 0x79b91d11, 0x9e13f3ff, 0x3f9b6bd9, 0xe173d136,
+ 0x695669d1, 0x697b3daf, 0x79b93a3a, 0x3f979f91,
+ 0x379ff976, 0xf99777fd, 0x9779737d, 0xe9d6bbf9,
+ 0xbfffd9df, 0x97f7fd97, 0x6f7b9bff, 0xf9bd9683,
+ 0x397db973, 0xd97b3b9f, 0xd7f9f733, 0x9993bb9e,
+ 0xe1f9ef93, 0x73773337, 0xb936917d, 0x11f87379,
+ 0xb979d336, 0x8b7ded73, 0x1b7d9337, 0x31f3f22f,
+ 0x3f2327ee, 0xeeeeeeee, 0xeeeeeeee, 0xeeeeeeee,
+ 0xeeeeee4b, 0xf4fbdbd2, 0x58bb1878, 0x577fdfd2,
+ 0xd573b773, 0xf7374b4f, 0xbdbd25b8, 0xb177d2d1,
+ 0x7376856b, 0xbfdd687b, 0xdd2fff8f, 0x78ffff8f,
+ 0xf22f0000,
+};
+#endif
static void UcodeCopy (volatile cpm8xx_t *cpm)
{
diff --git a/include/commproc.h b/include/commproc.h
index 53659c2..6b1b4e8 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -159,6 +159,8 @@ typedef struct smc_uart {
ushort smc_brkec; /* rcv'd break condition counter */
ushort smc_brkcr; /* xmt break count register */
ushort smc_rmask; /* Temporary bit mask */
+ u_char res1[8];
+ ushort smc_rpbase; /* Relocation pointer */
} smc_uart_t;
/* Function code bits.
--
1.5.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile.
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1 Heiko Schocher
@ 2008-01-11 0:12 ` Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [82xx] Fix defaultconfig for the mgcoge board Heiko Schocher
` (2 more replies)
2008-01-11 23:35 ` [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1 Wolfgang Denk
1 sibling, 3 replies; 14+ messages in thread
From: Heiko Schocher @ 2008-01-11 0:12 UTC (permalink / raw)
To: u-boot
Signed-off-by: Heiko Schocher <hs@denx.de>
---
MAKEALL | 1 +
Makefile | 3 +
board/mgcoge/Makefile | 50 +++++++
board/mgcoge/config.mk | 24 ++++
board/mgcoge/mgcoge.c | 345 ++++++++++++++++++++++++++++++++++++++++++++++
cpu/mpc8260/ether_scc.c | 9 +-
include/configs/mgcoge.h | 317 ++++++++++++++++++++++++++++++++++++++++++
7 files changed, 745 insertions(+), 4 deletions(-)
create mode 100644 board/mgcoge/Makefile
create mode 100644 board/mgcoge/config.mk
create mode 100644 board/mgcoge/mgcoge.c
create mode 100644 include/configs/mgcoge.h
diff --git a/MAKEALL b/MAKEALL
index 3224497..2ab67d1 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -281,6 +281,7 @@ LIST_8260=" \
hymod \
IPHASE4539 \
ISPAN \
+ mgcoge \
MPC8260ADS \
MPC8266ADS \
MPC8272ADS \
diff --git a/Makefile b/Makefile
index 7c1fbb8..5e67777 100644
--- a/Makefile
+++ b/Makefile
@@ -1539,6 +1539,9 @@ ISPAN_REVB_config: unconfig
fi
@$(MKCONFIG) -a ISPAN ppc mpc8260 ispan
+mgcoge_config : unconfig
+ @$(MKCONFIG) mgcoge ppc mpc8260 mgcoge
+
MPC8260ADS_config \
MPC8260ADS_lowboot_config \
MPC8260ADS_33MHz_config \
diff --git a/board/mgcoge/Makefile b/board/mgcoge/Makefile
new file mode 100644
index 0000000..1a14244
--- /dev/null
+++ b/board/mgcoge/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2007
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mgcoge/config.mk b/board/mgcoge/config.mk
new file mode 100644
index 0000000..143bc9f
--- /dev/null
+++ b/board/mgcoge/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2007
+# Heiko Schocher, DENX Software Engineering, hs at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFE000000
diff --git a/board/mgcoge/mgcoge.c b/board/mgcoge/mgcoge.c
new file mode 100644
index 0000000..0207a3a
--- /dev/null
+++ b/board/mgcoge/mgcoge.c
@@ -0,0 +1,345 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
+ /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
+ /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
+ /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
+ /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
+ /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
+ /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
+ /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
+ /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
+ /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
+ /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
+ /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
+ /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
+ /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
+ /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
+ /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
+ /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
+ /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
+ /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
+ /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
+ /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
+ /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
+ /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
+ /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
+ /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
+ /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
+ /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
+ /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
+ },
+
+ /* Port B */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
+ /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
+ /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
+ /* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
+ /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
+ /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
+ /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
+ /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
+ /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
+ /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
+ /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
+ /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
+ /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
+ /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
+ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
+ /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
+ /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
+ /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */
+ /* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */
+ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
+ /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
+ /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
+ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
+ /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
+ /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
+ /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
+ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
+ /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
+ /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
+ /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */
+ /* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */
+ /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
+ /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
+ /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
+ /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
+ /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
+ /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
+ /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
+ /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
+ /* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */
+ /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
+ /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
+ /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */
+ /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
+ /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
+ /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ }
+};
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+ ulong orx, volatile uchar * base)
+{
+ volatile uchar c = 0xff;
+ volatile uint *sdmr_ptr;
+ volatile uint *orx_ptr;
+ ulong maxsize, size;
+ int i;
+
+ /* We must be able to test a location outsize the maximum legal size
+ * to find out THAT we are outside; but this address still has to be
+ * mapped by the controller. That means, that the initial mapping has
+ * to be (at least) twice as large as the maximum expected size.
+ */
+ maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
+
+ sdmr_ptr = &memctl->memc_psdmr;
+ orx_ptr = &memctl->memc_or1;
+
+ *orx_ptr = orx;
+
+ /*
+ * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+ *
+ * "At system reset, initialization software must set up the
+ * programmable parameters in the memory controller banks registers
+ * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+ * system software should execute the following initialization sequence
+ * for each SDRAM device.
+ *
+ * 1. Issue a PRECHARGE-ALL-BANKS command
+ * 2. Issue eight CBR REFRESH commands
+ * 3. Issue a MODE-SET command to initialize the mode register
+ *
+ * The initial commands are executed by setting P/LSDMR[OP] and
+ * accessing the SDRAM with a single-byte transaction."
+ *
+ * The appropriate BRx/ORx registers have already been set when we
+ * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ */
+
+ *sdmr_ptr = sdmr | PSDMR_OP_PREA;
+ *base = c;
+
+ *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *base = c;
+
+ *sdmr_ptr = sdmr | PSDMR_OP_MRW;
+ *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
+
+ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ *base = c;
+
+ size = get_ram_size((long *)base, maxsize);
+ *orx_ptr = orx | ~(size - 1);
+
+ return (size);
+}
+
+long int initdram(int board_type)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+
+ long psize;
+
+ memctl->memc_psrt = CFG_PSRT;
+ memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+ /* 60x SDRAM setup:
+ */
+ psize = try_init (memctl, CFG_PSDMR, CFG_OR1,
+ (uchar *) CFG_SDRAM_BASE);
+#endif /* CFG_RAMBOOT */
+
+ icache_enable ();
+
+ return (psize);
+}
+
+int checkboard(void)
+{
+ puts("Board: mgcoge\n");
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+/*
+ * update "memory" property in the blob
+ */
+void ft_blob_update(void *blob, bd_t *bd)
+{
+ int ret, nodeoffset = 0;
+ ulong memory_data[2] = {0};
+ ulong flash_data[4] = {0};
+
+ memory_data[0] = cpu_to_be32(bd->bi_memstart);
+ memory_data[1] = cpu_to_be32(bd->bi_memsize);
+
+ nodeoffset = fdt_path_offset (blob, "/memory");
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
+ sizeof(memory_data));
+ if (ret < 0)
+ printf("ft_blob_update): cannot set /memory/reg "
+ "property err:%s\n", fdt_strerror(ret));
+ }
+ else {
+ /* memory node is required in dts */
+ printf("ft_blob_update(): cannot find /memory node "
+ "err:%s\n", fdt_strerror(nodeoffset));
+ }
+ /* update Flash size */
+ flash_data[2] = cpu_to_be32(bd->bi_flashstart);
+ flash_data[3] = cpu_to_be32(bd->bi_flashsize);
+ nodeoffset = fdt_path_offset (blob, "/localbus");
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data,
+ sizeof(flash_data));
+ if (ret < 0)
+ printf("ft_blob_update): cannot set /localbus/ranges "
+ "property err:%s\n", fdt_strerror(ret));
+ }
+ else {
+ /* memory node is required in dts */
+ printf("ft_blob_update(): cannot find /localbus node "
+ "err:%s\n", fdt_strerror(nodeoffset));
+ }
+ /* MAC Adresse */
+ nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet");
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr,
+ sizeof(uchar) * 6);
+ if (ret < 0)
+ printf("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address "
+ "property err:%s\n", fdt_strerror(ret));
+ }
+ else {
+ /* memory node is required in dts */
+ printf("ft_blob_update(): cannot find /localbus node "
+ "err:%s\n", fdt_strerror(nodeoffset));
+ }
+
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup( blob, bd);
+ ft_blob_update(blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c
index e56839d..633d053 100644
--- a/cpu/mpc8260/ether_scc.c
+++ b/cpu/mpc8260/ether_scc.c
@@ -77,7 +77,9 @@
#define TX_BUF_CNT 2
-#define TOUT_LOOP 1000000
+#if !defined(CFG_SCC_TOUT_LOOP)
+ #define CFG_SCC_TOUT_LOOP 1000000
+#endif
static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];
@@ -109,7 +111,7 @@ int eth_send(volatile void *packet, int length)
}
for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
- if (i >= TOUT_LOOP) {
+ if (i >= CFG_SCC_TOUT_LOOP) {
puts ("scc: tx buffer not ready\n");
goto out;
}
@@ -121,7 +123,7 @@ int eth_send(volatile void *packet, int length)
BD_ENET_TX_WRAP);
for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
- if (i >= TOUT_LOOP) {
+ if (i >= CFG_SCC_TOUT_LOOP) {
puts ("scc: tx error\n");
goto out;
}
@@ -262,7 +264,6 @@ int eth_init(bd_t *bis)
pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
-
/* 24.21 - (19): Initialize RxBD */
for (i = 0; i < PKTBUFSRX; i++)
{
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
new file mode 100644
index 0000000..ab28778
--- /dev/null
+++ b/include/configs/mgcoge.h
@@ -0,0 +1,317 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8247 1
+#define CONFIG_MPC8272_FAMILY 1
+#define CONFIG_MGCOGE 1
+
+#define CONFIG_CPM2 1 /* Has a CPM2 */
+
+#undef DEBUG
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define CONFIG_CONS_ON_SMC /* Console is on SMC */
+#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
+#undef CONFIG_CONS_NONE /* It's not on external UART */
+#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
+ */
+#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
+#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
+#undef CONFIG_ETHER_NONE /* No external Ethernet */
+
+#define CONFIG_ETHER_INDEX 4
+#define CFG_SCC_TOUT_LOOP 10000000
+
+# define CFG_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN 66000000 /* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "u-boot_addr=100000\0" \
+ "kernel_addr=200000\0" \
+ "fdt_addr=400000\0" \
+ "rootpath=/opt/eldk-4.2/ppc_82xx\0" \
+ "u-boot=/tftpboot/mgcoge/u-boot.bin\0" \
+ "bootfile=/tftpboot/mgcoge/uImage\0" \
+ "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \
+ "load=tftp ${u-boot_addr} ${u-boot}\0" \
+ "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \
+ "cp.b ${u-boot_addr} fe000000 ${filesize};" \
+ "prot on fe000000 fe03ffff\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addcon=setenv bootargs ${bootargs} console=ttyCPM0,,${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:on panic=1 " \
+ "console=${console}\0" \
+ "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
+ "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcon;"\
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "net_self=tftp ${kernel_addr} ${bootfile}; " \
+ "tftp ${fdt_addr} ${fdt_file}; " \
+ "tftp ${ramdisk_addr} ${ramdisk_file}; " \
+ "run ramargs addip; " \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFE000000
+#define CFG_FLASH_SIZE 32
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
+
+#define CFG_ENV_IS_IN_FLASH
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+#define CFG_IMMR 0xF0000000
+
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER 0x0604b211
+
+/* No slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CFG_HID2 0
+
+#define CFG_SIUMCR 0x4020c200
+#define CFG_SYPCR 0xFFFFFFC3
+#define CFG_BCR 0x10000000
+#define CFG_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR 0
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration 13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR 0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus Machine PortSz Device
+ * ---- --- ------- ------ ------
+ * 0 60x GPCM 8 bit FLASH
+ * 1 60x SDRAM 32 bit SDRAM
+ *
+ */
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
+ BRx_PS_8 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
+
+#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
+ ORxG_CSNT |\
+ ORxG_ACS_DIV2 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_TRLX )
+
+
+/* Bank 1 - 60x bus SDRAM
+ */
+#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
+#define CFG_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
+
+#define CFG_MPTPR 0x1800
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ */
+#define CFG_MRS_OFFS 0x00000110
+#define CFG_PSRT 0x0e
+
+#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
+ BRx_PS_64 |\
+ BRx_MS_SDRAM_P |\
+ BRx_V)
+
+#define CFG_OR1_PRELIM CFG_OR1
+
+/* SDRAM initialization values
+*/
+
+#define CFG_OR1 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+ ORxS_BPD_8 |\
+ ORxS_ROWST_PBI0_A7 |\
+ ORxS_NUMR_13)
+
+#define CFG_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
+ PSDMR_BSMA_A14_A16 |\
+ PSDMR_SDA10_PBI0_A9 |\
+ PSDMR_RFRC_5_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_2W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
+
+#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,8247 at 0"
+#define OF_SOC "soc@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc/cpm/serial at 11a90"
+
+#endif /* __CONFIG_H */
--
1.5.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 2/2] [82xx] Fix defaultconfig for the mgcoge board.
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile Heiko Schocher
@ 2008-01-11 0:12 ` Heiko Schocher
2008-01-11 23:35 ` Wolfgang Denk
2008-01-11 6:35 ` [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile Stefan Roese
2008-01-11 23:35 ` Wolfgang Denk
2 siblings, 1 reply; 14+ messages in thread
From: Heiko Schocher @ 2008-01-11 0:12 UTC (permalink / raw)
To: u-boot
Signed-off-by: Heiko Schocher <hs@denx.de>
---
include/configs/mgcoge.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index ab28778..3de2466 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -108,7 +108,7 @@
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:on panic=1 " \
+ "${netmask}:${hostname}:${netdev}:off panic=1 " \
"console=${console}\0" \
"net_nfs=tftp ${kernel_addr} ${bootfile}; " \
"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcon;"\
--
1.5.2.2
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile.
2008-01-11 0:12 [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1 Heiko Schocher
@ 2008-01-11 6:34 ` Stefan Roese
2008-01-11 23:38 ` Wolfgang Denk
2008-01-11 23:35 ` Wolfgang Denk
2 siblings, 1 reply; 14+ messages in thread
From: Stefan Roese @ 2008-01-11 6:34 UTC (permalink / raw)
To: u-boot
On Friday 11 January 2008, Heiko Schocher wrote:
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> MAKEALL | 1 +
> Makefile | 3 +
Please add an entry in MAINTAINERS too.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile.
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [82xx] Fix defaultconfig for the mgcoge board Heiko Schocher
@ 2008-01-11 6:35 ` Stefan Roese
2008-01-11 23:38 ` Wolfgang Denk
2008-01-11 23:35 ` Wolfgang Denk
2 siblings, 1 reply; 14+ messages in thread
From: Stefan Roese @ 2008-01-11 6:35 UTC (permalink / raw)
To: u-boot
On Friday 11 January 2008, Heiko Schocher wrote:
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> MAKEALL | 1 +
> Makefile | 3 +
Again, MAINTAINER entry missing.
Thanks.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile.
2008-01-11 0:12 [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1 Heiko Schocher
2008-01-11 6:34 ` [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile Stefan Roese
@ 2008-01-11 23:35 ` Wolfgang Denk
2 siblings, 0 replies; 14+ messages in thread
From: Wolfgang Denk @ 2008-01-11 23:35 UTC (permalink / raw)
To: u-boot
In message <1200010329-27543-1-git-send-email-hs@denx.de> you wrote:
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> MAKEALL | 1 +
> Makefile | 3 +
> board/mgsuvd/Makefile | 44 ++++++
> board/mgsuvd/config.mk | 28 ++++
> board/mgsuvd/mgsuvd.c | 216 ++++++++++++++++++++++++++++++
> board/mgsuvd/u-boot.lds | 144 ++++++++++++++++++++
> cpu/mpc8xx/cpu.c | 16 +++
> include/commproc.h | 26 ++++
> include/configs/mgsuvd.h | 325 ++++++++++++++++++++++++++++++++++++++++++++++
> 9 files changed, 803 insertions(+), 0 deletions(-)
> create mode 100644 board/mgsuvd/Makefile
> create mode 100644 board/mgsuvd/config.mk
> create mode 100644 board/mgsuvd/mgsuvd.c
> create mode 100644 board/mgsuvd/u-boot.lds
> create mode 100644 include/configs/mgsuvd.h
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Mike's Law: For a lumber company employing two men and a cut-off saw,
the marginal product of labor for any number of additional workers
equals zero until the acquisition of another cut-off saw. Let's not
even consider a chainsaw.
- Mike Dennison [You could always schedule the saw, though - ed.]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1.
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1 Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile Heiko Schocher
@ 2008-01-11 23:35 ` Wolfgang Denk
1 sibling, 0 replies; 14+ messages in thread
From: Wolfgang Denk @ 2008-01-11 23:35 UTC (permalink / raw)
To: u-boot
In message <1200010329-27543-2-git-send-email-hs@denx.de> you wrote:
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> README | 4 ++
> cpu/mpc8xx/cpu_init.c | 6 ++-
> cpu/mpc8xx/serial.c | 21 +++++++++++
> cpu/mpc8xx/upatch.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++-
> include/commproc.h | 2 +
> 5 files changed, 124 insertions(+), 3 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
... bacteriological warfare ... hard to believe we were once foolish
enough to play around with that.
-- McCoy, "The Omega Glory", stardate unknown
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile.
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [82xx] Fix defaultconfig for the mgcoge board Heiko Schocher
2008-01-11 6:35 ` [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile Stefan Roese
@ 2008-01-11 23:35 ` Wolfgang Denk
2 siblings, 0 replies; 14+ messages in thread
From: Wolfgang Denk @ 2008-01-11 23:35 UTC (permalink / raw)
To: u-boot
In message <1200010329-27543-3-git-send-email-hs@denx.de> you wrote:
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> MAKEALL | 1 +
> Makefile | 3 +
> board/mgcoge/Makefile | 50 +++++++
> board/mgcoge/config.mk | 24 ++++
> board/mgcoge/mgcoge.c | 345 ++++++++++++++++++++++++++++++++++++++++++++++
> cpu/mpc8260/ether_scc.c | 9 +-
> include/configs/mgcoge.h | 317 ++++++++++++++++++++++++++++++++++++++++++
> 7 files changed, 745 insertions(+), 4 deletions(-)
> create mode 100644 board/mgcoge/Makefile
> create mode 100644 board/mgcoge/config.mk
> create mode 100644 board/mgcoge/mgcoge.c
> create mode 100644 include/configs/mgcoge.h
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Knowledge, sir, should be free to all!
-- Harry Mudd, "I, Mudd", stardate 4513.3
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 2/2] [82xx] Fix defaultconfig for the mgcoge board.
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [82xx] Fix defaultconfig for the mgcoge board Heiko Schocher
@ 2008-01-11 23:35 ` Wolfgang Denk
0 siblings, 0 replies; 14+ messages in thread
From: Wolfgang Denk @ 2008-01-11 23:35 UTC (permalink / raw)
To: u-boot
In message <1200010329-27543-4-git-send-email-hs@denx.de> you wrote:
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> include/configs/mgcoge.h | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The speed of time is one second per second.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile.
2008-01-11 6:34 ` [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile Stefan Roese
@ 2008-01-11 23:38 ` Wolfgang Denk
2008-01-12 6:08 ` Heiko Schocher
0 siblings, 1 reply; 14+ messages in thread
From: Wolfgang Denk @ 2008-01-11 23:38 UTC (permalink / raw)
To: u-boot
In message <200801110734.34711.sr@denx.de> you wrote:
> On Friday 11 January 2008, Heiko Schocher wrote:
> > Signed-off-by: Heiko Schocher <hs@denx.de>
> > ---
> > MAKEALL | 1 +
> > Makefile | 3 +
>
> Please add an entry in MAINTAINERS too.
I did this for Heiko.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Unsichtbar macht sich die Dummheit, indem sie immer gr??ere Ausma?e
annimmt. -- Bertold Brecht: Der Tui-Roman
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile.
2008-01-11 6:35 ` [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile Stefan Roese
@ 2008-01-11 23:38 ` Wolfgang Denk
0 siblings, 0 replies; 14+ messages in thread
From: Wolfgang Denk @ 2008-01-11 23:38 UTC (permalink / raw)
To: u-boot
In message <200801110735.10317.sr@denx.de> you wrote:
> On Friday 11 January 2008, Heiko Schocher wrote:
> > Signed-off-by: Heiko Schocher <hs@denx.de>
> > ---
> > MAKEALL | 1 +
> > Makefile | 3 +
>
> Again, MAINTAINER entry missing.
I did this for Heiko.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Doubt is a pain too lonely to know that faith is his twin brother.
- Kahlil Gibran
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile.
2008-01-11 23:38 ` Wolfgang Denk
@ 2008-01-12 6:08 ` Heiko Schocher
2008-01-12 14:52 ` Wolfgang Denk
0 siblings, 1 reply; 14+ messages in thread
From: Heiko Schocher @ 2008-01-12 6:08 UTC (permalink / raw)
To: u-boot
Hello Wolfgang,
Wolfgang Denk wrote:
> In message <200801110734.34711.sr@denx.de> you wrote:
>> On Friday 11 January 2008, Heiko Schocher wrote:
>>> Signed-off-by: Heiko Schocher <hs@denx.de>
>>> ---
>>> MAKEALL | 1 +
>>> Makefile | 3 +
>> Please add an entry in MAINTAINERS too.
>
> I did this for Heiko.
Thanks! I mailed yesterday a Patch, but unfortunately I forgot the
list :-(, so just Stefan got the EMail ... here the patch:
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile.
2008-01-12 6:08 ` Heiko Schocher
@ 2008-01-12 14:52 ` Wolfgang Denk
0 siblings, 0 replies; 14+ messages in thread
From: Wolfgang Denk @ 2008-01-12 14:52 UTC (permalink / raw)
To: u-boot
Dear Heiko,
in message <4788594D.2040900@denx.de> you wrote:
>
> Subject: [PATCH] [MAINTAINER] Added MAINTAINER entry for the
> ids8247, jupiter, mgcoge, mgsuvd, municse,
> sc3 and uc101 boards.
>
> Signed-off-by: Heiko Schocher <hs@denx.de>
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
This all sounds complicated, but it mostly does excatly what you ex-
pect. It's just difficult for us to explain what you expect...
- L. Wall & R. L. Schwartz, _Programming Perl_
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2008-01-12 14:52 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-01-11 0:12 [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1 Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile Heiko Schocher
2008-01-11 0:12 ` [U-Boot-Users] [PATCH 2/2] [82xx] Fix defaultconfig for the mgcoge board Heiko Schocher
2008-01-11 23:35 ` Wolfgang Denk
2008-01-11 6:35 ` [U-Boot-Users] [PATCH 1/2] [82xx] Added support for the mgcoge board from keymile Stefan Roese
2008-01-11 23:38 ` Wolfgang Denk
2008-01-11 23:35 ` Wolfgang Denk
2008-01-11 23:35 ` [U-Boot-Users] [PATCH 2/2] [8xx] Enable SMC microcode relocation patch for SMC1 Wolfgang Denk
2008-01-11 6:34 ` [U-Boot-Users] [PATCH 1/2] [8xx] Added support for the mgsuvd board from keymile Stefan Roese
2008-01-11 23:38 ` Wolfgang Denk
2008-01-12 6:08 ` Heiko Schocher
2008-01-12 14:52 ` Wolfgang Denk
2008-01-11 23:35 ` Wolfgang Denk
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