[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Zhang Wei]

The patch adds the RapidIO framework into U-Boot. The board configuration
can be added into individual rio_init_board() function. Some functions
about RapidIO can be added later.

The support for Freescale PowerPC RapidIO controller is also added.

Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
---
 Makefile              |    1 +
 drivers/rio/Makefile  |   35 ++++++++++++++++++++++++++
 drivers/rio/fsl_rio.c |   64 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/rio/rio.c     |   65 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/common.h      |    3 ++
 include/rio.h         |   46 ++++++++++++++++++++++++++++++++++
 include/rio_ids.h     |    9 +++++++
 lib_ppc/board.c       |    5 ++++
 8 files changed, 228 insertions(+), 0 deletions(-)
 create mode 100644 drivers/rio/Makefile
 create mode 100644 drivers/rio/fsl_rio.c
 create mode 100644 drivers/rio/rio.c
 create mode 100644 include/rio.h
 create mode 100644 include/rio_ids.h

diff --git a/Makefile b/Makefile
index 1983ca0..1f3f26a 100644
--- a/Makefile
+++ b/Makefile
@@ -228,6 +228,7 @@ endif
 ifeq ($(CPU),mpc85xx)
 LIBS += drivers/qe/qe.a
 endif
+LIBS += drivers/rio/librio.a
 LIBS += drivers/rtc/librtc.a
 LIBS += drivers/serial/libserial.a
 LIBS += drivers/usb/libusb.a
diff --git a/drivers/rio/Makefile b/drivers/rio/Makefile
new file mode 100644
index 0000000..4b940c2
--- /dev/null
+++ b/drivers/rio/Makefile
@@ -0,0 +1,35 @@
+#
+# Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
+#
+# Author: Zhang Wei, wei.zhang at freescale.com, Jan 2008
+#
+# This is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB 	:= $(obj)librio.a
+
+COBJS-y += rio.o
+COBJS-y += fsl_rio.o
+
+COBJS	:= $(COBJS-y)
+SRCS 	:= $(COBJS:.o=.c)
+OBJS 	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/drivers/rio/fsl_rio.c b/drivers/rio/fsl_rio.c
new file mode 100644
index 0000000..c8bfa92
--- /dev/null
+++ b/drivers/rio/fsl_rio.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Zhang Wei, wei.zhang at freescale.com, Jan 2008
+ *
+ * Description:
+ * Freescale PowerPC RapidIO controller initialization file.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_RAPIDIO
+#include <command.h>
+#include <malloc.h>
+#include <rio.h>
+#include <rio_ids.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/immap_86xx.h>
+#include <asm/io.h>
+
+void fsl_rio_init(void *base, int busno)
+{
+	struct rio_dev *dev;
+	volatile ccsr_rio_t *rio = base;
+	struct rio_controller *hose;
+
+	dev = malloc(sizeof(struct rio_dev));
+	memset(dev, 0, sizeof(struct rio_dev));
+
+	dev->vendor = in_be32(&rio->didcar) & 0xffff;
+	dev->device = (in_be32(&rio->didcar) >> 16) & 0xffff;
+
+	hose = malloc(sizeof(struct rio_controller));
+	memset(hose, 0, sizeof(struct rio_controller));
+
+	INIT_LIST_HEAD(&hose->dev_list);
+	hose->busno = busno;
+	hose->base = base;
+	hose->self = dev;
+	list_add_tail(&hose->node, &rio_hose_list);
+
+	printf("RIO%d (%04x:%04x) on 0x%08x\n", hose->busno, dev->vendor,
+			dev->device, base);
+}
+
+void fsl_rio_quirk(struct rio_controller *hose, struct rio_dev *rdev)
+{
+#ifdef FSL_RIO_IP_V2
+	volatile ccsr_rio_t *rio = hose->base;
+	/* Set the controller to accept all packets
+	 * without checking the target ID
+	 */
+	out_be32(&rio->ptaacr, 1);
+#endif
+}
+#endif
diff --git a/drivers/rio/rio.c b/drivers/rio/rio.c
new file mode 100644
index 0000000..9391384
--- /dev/null
+++ b/drivers/rio/rio.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Zhang Wei, wei.zhang at freescale.com, Jun 2007
+ *
+ * Description:
+ * RapidIO initialization file.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_RAPIDIO
+
+#include <command.h>
+#include <linux/list.h>
+#include <rio.h>
+#include <rio_ids.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+struct list_head rio_hose_list;
+
+struct rio_quirk rio_post_quirk[] = {
+	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8548E, fsl_rio_quirk},
+	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8548, fsl_rio_quirk},
+	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8568E, fsl_rio_quirk},
+	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8568, fsl_rio_quirk},
+	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8641, fsl_rio_quirk},
+	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8641D, fsl_rio_quirk},
+	{},
+};
+
+void rio_hose_post(void)
+{
+	struct rio_controller *hose;
+	struct rio_quirk *post_quirk;
+
+	list_for_each_entry(hose, &rio_hose_list, node)
+		for (post_quirk = rio_post_quirk;
+		     post_quirk->vendor || post_quirk->device; post_quirk++)
+			if ((post_quirk->vendor == hose->self->vendor)
+				  && (post_quirk->device == hose->self->device)
+				  && post_quirk->quirk) {
+				post_quirk->quirk(hose, hose->self);
+				break;
+			}
+}
+
+void rio_init(void)
+{
+	INIT_LIST_HEAD(&rio_hose_list);
+
+	/* Call board specific rio_init() */
+	rio_init_board();
+
+	rio_hose_post();
+}
+
+#endif /* CONFIG_RAPIDIO */
diff --git a/include/common.h b/include/common.h
index 9ef9344..84ff943 100644
--- a/include/common.h
+++ b/include/common.h
@@ -275,6 +275,9 @@ void	pciinfo	      (int, int);
 #endif
 #endif
 
+void	rio_init      (void);
+void	rio_init_board(void);
+
 int	misc_init_f   (void);
 int	misc_init_r   (void);
 
diff --git a/include/rio.h b/include/rio.h
new file mode 100644
index 0000000..379c56c
--- /dev/null
+++ b/include/rio.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __INCLUDE_RIO_H_
+#define __INCLUDE_RIO_H_
+
+#include <linux/list.h>
+
+struct rio_dev {
+	struct list_head	node;
+	u16			vendor;		/* Vendor ID */
+	u16			device;		/* Device ID */
+
+	u32			devno;		/* Device number */
+	u32			hostno;		/* Host number in the bus */
+};
+
+struct rio_controller {
+	struct list_head	node;
+	struct list_head	dev_list;
+
+	int			busno;
+
+	struct rio_dev		*self;	/* Controler RIO device */
+	void			*base;	/* Register base */
+};
+
+struct rio_quirk {
+	u16	vendor;
+	u16	device;
+	void	(*quirk)(struct rio_controller *hose, struct rio_dev *dev);
+};
+
+void fsl_rio_init(void *base, int busno);
+void fsl_rio_quirk(struct rio_controller *hose, struct rio_dev *rdev);
+
+extern struct list_head rio_hose_list;
+
+#endif /* __INCLUDE_RIO_H_ */
diff --git a/include/rio_ids.h b/include/rio_ids.h
new file mode 100644
index 0000000..b6a4ab8
--- /dev/null
+++ b/include/rio_ids.h
@@ -0,0 +1,9 @@
+
+#define RIO_VENDOR_ID_FREESCALE	0x0002
+
+#define RIO_DEVICE_ID_MPC8548E	0x0012
+#define RIO_DEVICE_ID_MPC8548	0x0013
+#define RIO_DEVICE_ID_MPC8568E	0x0020
+#define RIO_DEVICE_ID_MPC8568	0x0021
+#define RIO_DEVICE_ID_MPC8641	0x7010
+#define RIO_DEVICE_ID_MPC8641D	0x7011
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 0719745..75746ff 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -921,6 +921,11 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	pci_init ();
 #endif
 
+#if defined(CONFIG_RAPIDIO)
+	/* Do RapidIO configuration */
+	rio_init ();
+#endif
+
 /** leave this here (after malloc(), environment and PCI are working) **/
 	/* Initialize devices */
 	devices_init ();
-- 
1.5.2

[U-Boot-Users] [PATCH 2/3] Fixed the error in immap RapidIO definition.

[Zhang Wei]

Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
---
 include/asm-ppc/immap_85xx.h    |  169 +---------------
 include/asm-ppc/immap_86xx.h    |  232 +---------------------
 include/asm-ppc/immap_fsl_rio.h |  426 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 428 insertions(+), 399 deletions(-)
 create mode 100644 include/asm-ppc/immap_fsl_rio.h

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index d769d70..7d8522b 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -13,6 +13,7 @@
 
 #include <asm/types.h>
 #include <asm/fsl_i2c.h>
+#include <asm/immap_fsl_rio.h>
 
 /*
  * Local-Access Registers and ECM Registers(0x0000-0x2000)
@@ -1353,174 +1354,6 @@ typedef struct ccsr_cpm {
 } ccsr_cpm_t;
 #endif
 
-/*
- * RapidIO Registers(0xc_0000-0xe_0000)
- */
-typedef struct ccsr_rio {
-	uint	didcar;		/* 0xc0000 - Device Identity Capability Register */
-	uint	dicar;		/* 0xc0004 - Device Information Capability Register */
-	uint	aidcar;		/* 0xc0008 - Assembly Identity Capability Register */
-	uint	aicar;		/* 0xc000c - Assembly Information Capability Register */
-	uint	pefcar;		/* 0xc0010 - Processing Element Features Capability Register */
-	uint	spicar;		/* 0xc0014 - Switch Port Information Capability Register */
-	uint	socar;		/* 0xc0018 - Source Operations Capability Register */
-	uint	docar;		/* 0xc001c - Destination Operations Capability Register */
-	char	res1[32];
-	uint	msr;		/* 0xc0040 - Mailbox Command And Status Register */
-	uint	pwdcsr;		/* 0xc0044 - Port-Write and Doorbell Command And Status Register */
-	char	res2[4];
-	uint	pellccsr;	/* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
-	char	res3[12];
-	uint	lcsbacsr;	/* 0xc005c - Local Configuration Space Base Address Command and Status Register */
-	uint	bdidcsr;	/* 0xc0060 - Base Device ID Command and Status Register */
-	char	res4[4];
-	uint	hbdidlcsr;	/* 0xc0068 - Host Base Device ID Lock Command and Status Register */
-	uint	ctcsr;		/* 0xc006c - Component Tag Command and Status Register */
-	char	res5[144];
-	uint	pmbh0csr;	/* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
-	char	res6[28];
-	uint	pltoccsr;	/* 0xc0120 - Port Link Time-out Control Command and Status Register */
-	uint	prtoccsr;	/* 0xc0124 - Port Response Time-out Control Command and Status Register */
-	char	res7[20];
-	uint	pgccsr;		/* 0xc013c - Port General Command and Status Register */
-	uint	plmreqcsr;	/* 0xc0140 - Port Link Maintenance Request Command and Status Register */
-	uint	plmrespcsr;	/* 0xc0144 - Port Link Maintenance Response Command and Status Register */
-	uint	plascsr;	/* 0xc0148 - Port Local Ackid Status Command and Status Register */
-	char	res8[12];
-	uint	pescsr;		/* 0xc0158 - Port Error and Status Command and Status Register */
-	uint	pccsr;		/* 0xc015c - Port Control Command and Status Register */
-	char	res9[65184];
-	uint	cr;		/* 0xd0000 - Port Control Command and Status Register */
-	char	res10[12];
-	uint	pcr;		/* 0xd0010 - Port Configuration Register */
-	uint	peir;		/* 0xd0014 - Port Error Injection Register */
-	char	res11[3048];
-	uint	rowtar0;	/* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
-	char	res12[12];
-	uint	rowar0;		/* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
-	char	res13[12];
-	uint	rowtar1;	/* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
-	char	res14[4];
-	uint	rowbar1;	/* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
-	char	res15[4];
-	uint	rowar1;		/* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
-	char	res16[12];
-	uint	rowtar2;	/* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
-	char	res17[4];
-	uint	rowbar2;	/* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
-	char	res18[4];
-	uint	rowar2;		/* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
-	char	res19[12];
-	uint	rowtar3;	/* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
-	char	res20[4];
-	uint	rowbar3;	/* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
-	char	res21[4];
-	uint	rowar3;		/* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
-	char	res22[12];
-	uint	rowtar4;	/* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
-	char	res23[4];
-	uint	rowbar4;	/* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
-	char	res24[4];
-	uint	rowar4;		/* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
-	char	res25[12];
-	uint	rowtar5;	/* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
-	char	res26[4];
-	uint	rowbar5;	/* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
-	char	res27[4];
-	uint	rowar5;		/* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
-	char	res28[12];
-	uint	rowtar6;	/* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
-	char	res29[4];
-	uint	rowbar6;	/* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
-	char	res30[4];
-	uint	rowar6;		/* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
-	char	res31[12];
-	uint	rowtar7;	/* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
-	char	res32[4];
-	uint	rowbar7;	/* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
-	char	res33[4];
-	uint	rowar7;		/* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
-	char	res34[12];
-	uint	rowtar8;	/* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
-	char	res35[4];
-	uint	rowbar8;	/* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
-	char	res36[4];
-	uint	rowar8;		/* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
-	char	res37[76];
-	uint	riwtar4;	/* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
-	char	res38[4];
-	uint	riwbar4;	/* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
-	char	res39[4];
-	uint	riwar4;		/* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
-	char	res40[12];
-	uint	riwtar3;	/* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
-	char	res41[4];
-	uint	riwbar3;	/* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
-	char	res42[4];
-	uint	riwar3;		/* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
-	char	res43[12];
-	uint	riwtar2;	/* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
-	char	res44[4];
-	uint	riwbar2;	/* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
-	char	res45[4];
-	uint	riwar2;		/* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
-	char	res46[12];
-	uint	riwtar1;	/* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
-	char	res47[4];
-	uint	riwbar1;	/* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
-	char	res48[4];
-	uint	riwar1;		/* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
-	char	res49[12];
-	uint	riwtar0;	/* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
-	char	res50[12];
-	uint	riwar0;		/* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
-	char	res51[12];
-	uint	pnfedr;		/* 0xd0e00 - Port Notification/Fatal Error Detect Register */
-	uint	pnfedir;	/* 0xd0e04 - Port Notification/Fatal Error Detect Register */
-	uint	pnfeier;	/* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
-	uint	pecr;		/* 0xd0e0c - Port Error Control Register */
-	uint	pepcsr0;	/* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
-	uint	pepr1;		/* 0xd0e14 - Port Error Packet Register 1 */
-	uint	pepr2;		/* 0xd0e18 - Port Error Packet Register 2 */
-	char	res52[4];
-	uint	predr;		/* 0xd0e20 - Port Recoverable Error Detect Register */
-	char	res53[4];
-	uint	pertr;		/* 0xd0e28 - Port Error Recovery Threshold Register */
-	uint	prtr;		/* 0xd0e2c - Port Retry Threshold Register */
-	char	res54[464];
-	uint	omr;		/* 0xd1000 - Outbound Mode Register */
-	uint	osr;		/* 0xd1004 - Outbound Status Register */
-	uint	eodqtpar;	/* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
-	uint	odqtpar;	/* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
-	uint	eosar;		/* 0xd1010 - Extended Outbound Unit Source Address Register */
-	uint	osar;		/* 0xd1014 - Outbound Unit Source Address Register */
-	uint	odpr;		/* 0xd1018 - Outbound Destination Port Register */
-	uint	odatr;		/* 0xd101c - Outbound Destination Attributes Register */
-	uint	odcr;		/* 0xd1020 - Outbound Doubleword Count Register */
-	uint	eodqhpar;	/* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
-	uint	odqhpar;	/* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
-	char	res55[52];
-	uint	imr;		/* 0xd1060 - Outbound Mode Register */
-	uint	isr;		/* 0xd1064 - Inbound Status Register */
-	uint	eidqtpar;	/* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
-	uint	idqtpar;	/* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
-	uint	eifqhpar;	/* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
-	uint	ifqhpar;	/* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
-	char	res56[1000];
-	uint	dmr;		/* 0xd1460 - Doorbell Mode Register */
-	uint	dsr;		/* 0xd1464 - Doorbell Status Register */
-	uint	edqtpar;	/* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
-	uint	dqtpar;		/* 0xd146c - Doorbell Queue Tail Pointer Address Register */
-	uint	edqhpar;	/* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
-	uint	dqhpar;		/* 0xd1474 - Doorbell Queue Head Pointer Address Register */
-	char	res57[104];
-	uint	pwmr;		/* 0xd14e0 - Port-Write Mode Register */
-	uint	pwsr;		/* 0xd14e4 - Port-Write Status Register */
-	uint	epwqbar;	/* 0xd14e8 - Extended Port-Write Queue Base Address Register */
-	uint	pwqbar;		/* 0xd14ec - Port-Write Queue Base Address Register */
-	char	res58[60176];
-} ccsr_rio_t;
-
 /* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
 typedef struct par_io {
 	uint	cpodr;		/* 0x100 */
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 169725b..dfcd61a 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -12,6 +12,7 @@
 
 #include <asm/types.h>
 #include <asm/fsl_i2c.h>
+#include <asm/immap_fsl_rio.h>
 
 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
 typedef struct ccsr_local_mcm {
@@ -1020,237 +1021,6 @@ typedef struct ccsr_pic {
 	char	res158[3916];
 } ccsr_pic_t;
 
-/* RapidIO Registers(0xc_0000-0xe_0000) */
-
-typedef struct ccsr_rio {
-	uint	didcar;		/* 0xc0000 - Device Identity Capability Register */
-	uint	dicar;		/* 0xc0004 - Device Information Capability Register */
-	uint	aidcar;		/* 0xc0008 - Assembly Identity Capability Register */
-	uint	aicar;		/* 0xc000c - Assembly Information Capability Register */
-	uint	pefcar;		/* 0xc0010 - Processing Element Features Capability Register */
-	uint	spicar;		/* 0xc0014 - Switch Port Information Capability Register */
-	uint	socar;		/* 0xc0018 - Source Operations Capability Register */
-	uint	docar;		/* 0xc001c - Destination Operations Capability Register */
-	char	res1[32];
-	uint	msr;		/* 0xc0040 - Mailbox Command And Status Register */
-	uint	pwdcsr;		/* 0xc0044 - Port-Write and Doorbell Command And Status Register */
-	char	res2[4];
-	uint	pellccsr;	/* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
-	char	res3[12];
-	uint	lcsbacsr;	/* 0xc005c - Local Configuration Space Base Address Command and Status Register */
-	uint	bdidcsr;	/* 0xc0060 - Base Device ID Command and Status Register */
-	char	res4[4];
-	uint	hbdidlcsr;	/* 0xc0068 - Host Base Device ID Lock Command and Status Register */
-	uint	ctcsr;		/* 0xc006c - Component Tag Command and Status Register */
-	char	res5[144];
-	uint	pmbh0csr;	/* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
-	char	res6[28];
-	uint	pltoccsr;	/* 0xc0120 - Port Link Time-out Control Command and Status Register */
-	uint	prtoccsr;	/* 0xc0124 - Port Response Time-out Control Command and Status Register */
-	char	res7[20];
-	uint	pgccsr;		/* 0xc013c - Port General Command and Status Register */
-	uint	plmreqcsr;	/* 0xc0140 - Port Link Maintenance Request Command and Status Register */
-	uint	plmrespcsr;	/* 0xc0144 - Port Link Maintenance Response Command and Status Register */
-	uint	plascsr;	/* 0xc0148 - Port Local Ackid Status Command and Status Register */
-	char	res8[12];
-	uint	pescsr;		/* 0xc0158 - Port Error and Status Command and Status Register */
-	uint	pccsr;		/* 0xc015c - Port Control Command and Status Register */
-	char	res9[1184];
-	uint	erbh;		/* 0xc0600 - Error Reporting Block Header Register */
-	char	res10[4];
-	uint	ltledcsr;	/* 0xc0608 - Logical/Transport layer error detect status register */
-	uint	ltleecsr;	/* 0xc060c - Logical/Transport layer error enable register */
-	char	res11[4];
-	uint	ltlaccsr;	/* 0xc0614 - Logical/Transport layer addresss capture register */
-	uint	ltldidccsr;	/* 0xc0618 - Logical/Transport layer device ID capture register */
-	uint	ltlcccsr;	/* 0xc061c - Logical/Transport layer control capture register */
-	char	res12[32];
-	uint	edcsr;	        /* 0xc0640 - Port 0 error detect status register */
-	uint	erecsr;	        /* 0xc0644 - Port 0 error rate enable status register */
-	uint	ecacsr;	        /* 0xc0648 - Port 0 error capture attributes register */
-	uint	pcseccsr0;	/* 0xc064c - Port 0 packet/control symbol error capture register 0 */
-	uint	peccsr1;	/* 0xc0650 - Port 0 error capture command and status register 1 */
-	uint	peccsr2;	/* 0xc0654 - Port 0 error capture command and status register 2 */
-	uint	peccsr3;	/* 0xc0658 - Port 0 error capture command and status register 3 */
-	char	res13[12];
-	uint	ercsr;	        /* 0xc0668 - Port 0 error rate command and status register */
-	uint	ertcsr;	        /* 0xc066C - Port 0 error rate threshold status register*/
-	char	res14[63892];
-	uint	llcr;		/* 0xd0004 - Logical Layer Configuration Register */
-	char	res15[12];
-	uint	epwisr;		/* 0xd0010 - Error / Port-Write Interrupt Status Register */
-	char	res16[12];
-	uint	lretcr;		/* 0xd0020 - Logical Retry Error Threshold Configuration Register */
-	char	res17[92];
-	uint	pretcr;		/* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
-	char	res18[124];
-	uint	adidcsr;	/* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
-	char	res19[28];
-	uint	ptaacr;	        /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
-	char	res20[12];
-	uint	iecsr;	        /* 0xd0130 - Port 0 Implementation Error Status Register */
-	char	res21[12];
-	uint	pcr;		/* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
-	char	res22[20];
-	uint	slcsr;	        /* 0xd0158 - Port 0 Serial Link Command and Status Register */
-	char	res23[4];
-	uint	sleir;	        /* 0xd0160 - Port 0 Serial Link Error Injection Register */
-	char	res24[2716];
-	uint	rowtar0;	/* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
-	uint	rowtear0;	/* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
-	char	res25[8];
-	uint	rowar0;		/* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
-	char	res26[12];
-	uint	rowtar1;	/* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
-	uint	rowtear1;	/* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
-	uint	rowbar1;	/* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
-	char	res27[4];
-	uint	rowar1;		/* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
-	uint	rows1r1;	/* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
-	uint	rows2r1;	/* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
-	uint	rows3r1;	/* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
-	uint	rowtar2;	/* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
-	uint	rowtear2;	/* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
-	uint	rowbar2;	/* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
-	char	res28[4];
-	uint	rowar2;		/* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
-	uint	rows1r2;	/* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
-	uint	rows2r2;	/* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
-	uint	rows3r2;	/* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
-	uint	rowtar3;	/* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
-	uint	rowtear3;	/* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
-	uint	rowbar3;	/* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
-	char	res29[4];
-	uint	rowar3;		/* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
-	uint	rows1r3;	/* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
-	uint	rows2r3;	/* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
-	uint	rows3r3;	/* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
-	uint	rowtar4;	/* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
-	uint	rowtear4;	/* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
-	uint	rowbar4;	/* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
-	char	res30[4];
-	uint	rowar4;		/* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
-	uint	rows1r4;	/* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
-	uint	rows2r4;	/* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
-	uint	rows3r4;	/* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
-	uint	rowtar5;	/* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
-	uint	rowtear5;	/* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
-	uint	rowbar5;	/* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
-	char	res31[4];
-	uint	rowar5;		/* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
-	uint	rows1r5;	/* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
-	uint	rows2r5;	/* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
-	uint	rows3r5;	/* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
-	uint	rowtar6;	/* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
-	uint	rowtear6;	/* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
-	uint	rowbar6;	/* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
-	char	res32[4];
-	uint	rowar6;		/* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
-	uint	rows1r6;	/* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
-	uint	rows2r6;	/* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
-	uint	rows3r6;	/* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
-	uint	rowtar7;	/* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
-	uint	rowtear7;	/* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
-	uint	rowbar7;	/* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
-	char	res33[4];
-	uint	rowar7;		/* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
-	uint	rows1r7;	/* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
-	uint	rows2r7;	/* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
-	uint	rows3r7;	/* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
-	uint	rowtar8;	/* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
-	uint	rowtear8;	/* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
-	uint	rowbar8;	/* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
-	char	res34[4];
-	uint	rowar8;		/* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
-	uint	rows1r8;	/* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
-	uint	rows2r8;	/* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
-	uint	rows3r8;	/* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
-	char	res35[64];
-	uint	riwtar4;	/* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
-	uint	riwbar4;	/* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
-	char	res36[4];
-	uint	riwar4;		/* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
-	char	res37[12];
-	uint	riwtar3;	/* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
-	char	res38[4];
-	uint	riwbar3;	/* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
-	char	res39[4];
-	uint	riwar3;		/* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
-	char	res40[12];
-	uint	riwtar2;	/* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
-	char	res41[4];
-	uint	riwbar2;	/* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
-	char	res42[4];
-	uint	riwar2;		/* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
-	char	res43[12];
-	uint	riwtar1;	/* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
-	char	res44[4];
-	uint	riwbar1;	/* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
-	char	res45[4];
-	uint	riwar1;		/* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
-	char	res46[12];
-	uint	riwtar0;	/* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
-	char	res47[12];
-	uint	riwar0;		/* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
-	char	res48[12];
-	uint	pnfedr;		/* 0xd0e00 - Port Notification/Fatal Error Detect Register */
-	uint	pnfedir;	/* 0xd0e04 - Port Notification/Fatal Error Detect Register */
-	uint	pnfeier;	/* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
-	uint	pecr;		/* 0xd0e0c - Port Error Control Register */
-	uint	pepcsr0;	/* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
-	uint	pepr1;		/* 0xd0e14 - Port Error Packet Register 1 */
-	uint	pepr2;		/* 0xd0e18 - Port Error Packet Register 2 */
-	char	res49[4];
-	uint	predr;		/* 0xd0e20 - Port Recoverable Error Detect Register */
-	char	res50[4];
-	uint	pertr;		/* 0xd0e28 - Port Error Recovery Threshold Register */
-	uint	prtr;		/* 0xd0e2c - Port Retry Threshold Register */
-	char	res51[8656];
-	uint	omr;		/* 0xd3000 - Outbound Mode Register */
-	uint	osr;		/* 0xd3004 - Outbound Status Register */
-	uint	eodqtpar;	/* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
-	uint	odqtpar;	/* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
-	uint	eosar;		/* 0xd3010 - Extended Outbound Unit Source Address Register */
-	uint	osar;		/* 0xd3014 - Outbound Unit Source Address Register */
-	uint	odpr;		/* 0xd3018 - Outbound Destination Port Register */
-	uint	odatr;		/* 0xd301c - Outbound Destination Attributes Register */
-	uint	odcr;		/* 0xd3020 - Outbound Doubleword Count Register */
-	uint	eodqhpar;	/* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
-	uint	odqhpar;	/* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
-	uint	oretr;	        /* 0xd302C - Outbound Retry Error Threshold Register */
-	uint	omgr;	        /* 0xd3030 - Outbound Multicast Group Register */
-	uint	omlr;	        /* 0xd3034 - Outbound Multicast List Register */
-	char	res52[40];
-	uint	imr;		/* 0xd3060 - Outbound Mode Register */
-	uint	isr;		/* 0xd3064 - Inbound Status Register */
-	uint	eidqtpar;	/* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
-	uint	idqtpar;	/* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
-	uint	eifqhpar;	/* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
-	uint	ifqhpar;	/* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
-	uint	imirir;	        /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
-	char	res53[900];
-	uint	oddmr;		/* 0xd3400 - Outbound Doorbell Mode Register */
-	uint	oddsr;		/* 0xd3404 - Outbound Doorbell Status Register */
-	char	res54[16];
-	uint	oddpr;		/* 0xd3418 - Outbound Doorbell Destination Port Register */
-	uint	oddatr;		/* 0xd341C - Outbound Doorbell Destination Attributes Register */
-	char	res55[12];
-	uint	oddretr;	/* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
-	char	res56[48];
-	uint	idmr;		/* 0xd3460 - Inbound Doorbell Mode Register */
-	uint	idsr;		/* 0xd3464 - Inbound Doorbell Status Register */
-	uint	iedqtpar;	/* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
-	uint	iqtpar;	        /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
-	uint	iedqhpar;	/* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
-	uint	idqhpar;	/* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
-	uint	idmirir;	/* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
-	char	res57[100];
-	uint	pwmr;		/* 0xd34e0 - Port-Write Mode Register */
-	uint	pwsr;		/* 0xd34e4 - Port-Write Status Register */
-	uint	epwqbar;	/* 0xd34e8 - Extended Port-Write Queue Base Address Register */
-	uint	pwqbar;		/* 0xd34ec - Port-Write Queue Base Address Register */
-	char	res58[51984];
-} ccsr_rio_t;
 
 /* Global Utilities Register Block(0xe_0000-0xf_ffff) */
 typedef struct ccsr_gur {
diff --git a/include/asm-ppc/immap_fsl_rio.h b/include/asm-ppc/immap_fsl_rio.h
new file mode 100644
index 0000000..d2aca83
--- /dev/null
+++ b/include/asm-ppc/immap_fsl_rio.h
@@ -0,0 +1,426 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_PPC_IMMAP_FSL_RIO_H_
+#define __ASM_PPC_IMMAP_FSL_RIO_H_
+
+#undef FSL_RIO_IP_V1
+#undef FSL_RIO_IP_V2
+
+#if defined(CONFIG_MPC8540) | defined(CONFIG_MPC8560)
+#define FSL_RIO_IP_V1
+#else
+#define FSL_RIO_IP_V2
+#endif
+
+#ifdef FSL_RIO_IP_V1
+
+/* RapidIO Register for IP version 1 */
+typedef struct ccsr_rio {
+	uint	didcar;		/* 0xc0000 - Device Identity Capability Register */
+	uint	dicar;		/* 0xc0004 - Device Information Capability Register */
+	uint	aidcar;		/* 0xc0008 - Assembly Identity Capability Register */
+	uint	aicar;		/* 0xc000c - Assembly Information Capability Register */
+	uint	pefcar;		/* 0xc0010 - Processing Element Features Capability Register */
+	uint	spicar;		/* 0xc0014 - Switch Port Information Capability Register */
+	uint	socar;		/* 0xc0018 - Source Operations Capability Register */
+	uint	docar;		/* 0xc001c - Destination Operations Capability Register */
+	char	res1[32];
+	uint	msr;		/* 0xc0040 - Mailbox Command And Status Register */
+	uint	pwdcsr;		/* 0xc0044 - Port-Write and Doorbell Command And Status Register */
+	char	res2[4];
+	uint	pellccsr;	/* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
+	char	res3[12];
+	uint	lcsbacsr;	/* 0xc005c - Local Configuration Space Base Address Command and Status Register */
+	uint	bdidcsr;	/* 0xc0060 - Base Device ID Command and Status Register */
+	char	res4[4];
+	uint	hbdidlcsr;	/* 0xc0068 - Host Base Device ID Lock Command and Status Register */
+	uint	ctcsr;		/* 0xc006c - Component Tag Command and Status Register */
+	char	res5[144];
+	uint	pmbh0csr;	/* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
+	char	res6[28];
+	uint	pltoccsr;	/* 0xc0120 - Port Link Time-out Control Command and Status Register */
+	uint	prtoccsr;	/* 0xc0124 - Port Response Time-out Control Command and Status Register */
+	char	res7[20];
+	uint	pgccsr;		/* 0xc013c - Port General Command and Status Register */
+	uint	plmreqcsr;	/* 0xc0140 - Port Link Maintenance Request Command and Status Register */
+	uint	plmrespcsr;	/* 0xc0144 - Port Link Maintenance Response Command and Status Register */
+	uint	plascsr;	/* 0xc0148 - Port Local Ackid Status Command and Status Register */
+	char	res8[12];
+	uint	pescsr;		/* 0xc0158 - Port Error and Status Command and Status Register */
+	uint	pccsr;		/* 0xc015c - Port Control Command and Status Register */
+	char	res9[65184];
+	uint	cr;		/* 0xd0000 - Port Control Command and Status Register */
+	char	res10[12];
+	uint	pcr;		/* 0xd0010 - Port Configuration Register */
+	uint	peir;		/* 0xd0014 - Port Error Injection Register */
+	char	res11[3048];
+	uint	rowtar0;	/* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
+	char	res12[12];
+	uint	rowar0;		/* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
+	char	res13[12];
+	uint	rowtar1;	/* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
+	char	res14[4];
+	uint	rowbar1;	/* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
+	char	res15[4];
+	uint	rowar1;		/* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
+	char	res16[12];
+	uint	rowtar2;	/* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
+	char	res17[4];
+	uint	rowbar2;	/* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
+	char	res18[4];
+	uint	rowar2;		/* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
+	char	res19[12];
+	uint	rowtar3;	/* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
+	char	res20[4];
+	uint	rowbar3;	/* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
+	char	res21[4];
+	uint	rowar3;		/* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
+	char	res22[12];
+	uint	rowtar4;	/* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
+	char	res23[4];
+	uint	rowbar4;	/* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
+	char	res24[4];
+	uint	rowar4;		/* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
+	char	res25[12];
+	uint	rowtar5;	/* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
+	char	res26[4];
+	uint	rowbar5;	/* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
+	char	res27[4];
+	uint	rowar5;		/* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
+	char	res28[12];
+	uint	rowtar6;	/* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
+	char	res29[4];
+	uint	rowbar6;	/* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
+	char	res30[4];
+	uint	rowar6;		/* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
+	char	res31[12];
+	uint	rowtar7;	/* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
+	char	res32[4];
+	uint	rowbar7;	/* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
+	char	res33[4];
+	uint	rowar7;		/* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
+	char	res34[12];
+	uint	rowtar8;	/* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
+	char	res35[4];
+	uint	rowbar8;	/* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
+	char	res36[4];
+	uint	rowar8;		/* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
+	char	res37[76];
+	uint	riwtar4;	/* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
+	char	res38[4];
+	uint	riwbar4;	/* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
+	char	res39[4];
+	uint	riwar4;		/* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
+	char	res40[12];
+	uint	riwtar3;	/* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
+	char	res41[4];
+	uint	riwbar3;	/* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
+	char	res42[4];
+	uint	riwar3;		/* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
+	char	res43[12];
+	uint	riwtar2;	/* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
+	char	res44[4];
+	uint	riwbar2;	/* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
+	char	res45[4];
+	uint	riwar2;		/* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
+	char	res46[12];
+	uint	riwtar1;	/* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
+	char	res47[4];
+	uint	riwbar1;	/* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
+	char	res48[4];
+	uint	riwar1;		/* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
+	char	res49[12];
+	uint	riwtar0;	/* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
+	char	res50[12];
+	uint	riwar0;		/* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
+	char	res51[12];
+	uint	pnfedr;		/* 0xd0e00 - Port Notification/Fatal Error Detect Register */
+	uint	pnfedir;	/* 0xd0e04 - Port Notification/Fatal Error Detect Register */
+	uint	pnfeier;	/* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
+	uint	pecr;		/* 0xd0e0c - Port Error Control Register */
+	uint	pepcsr0;	/* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
+	uint	pepr1;		/* 0xd0e14 - Port Error Packet Register 1 */
+	uint	pepr2;		/* 0xd0e18 - Port Error Packet Register 2 */
+	char	res52[4];
+	uint	predr;		/* 0xd0e20 - Port Recoverable Error Detect Register */
+	char	res53[4];
+	uint	pertr;		/* 0xd0e28 - Port Error Recovery Threshold Register */
+	uint	prtr;		/* 0xd0e2c - Port Retry Threshold Register */
+	char	res54[464];
+	uint	omr;		/* 0xd1000 - Outbound Mode Register */
+	uint	osr;		/* 0xd1004 - Outbound Status Register */
+	uint	eodqtpar;	/* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
+	uint	odqtpar;	/* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
+	uint	eosar;		/* 0xd1010 - Extended Outbound Unit Source Address Register */
+	uint	osar;		/* 0xd1014 - Outbound Unit Source Address Register */
+	uint	odpr;		/* 0xd1018 - Outbound Destination Port Register */
+	uint	odatr;		/* 0xd101c - Outbound Destination Attributes Register */
+	uint	odcr;		/* 0xd1020 - Outbound Doubleword Count Register */
+	uint	eodqhpar;	/* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
+	uint	odqhpar;	/* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
+	char	res55[52];
+	uint	imr;		/* 0xd1060 - Outbound Mode Register */
+	uint	isr;		/* 0xd1064 - Inbound Status Register */
+	uint	eidqtpar;	/* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
+	uint	idqtpar;	/* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
+	uint	eifqhpar;	/* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
+	uint	ifqhpar;	/* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
+	char	res56[1000];
+	uint	dmr;		/* 0xd1460 - Doorbell Mode Register */
+	uint	dsr;		/* 0xd1464 - Doorbell Status Register */
+	uint	edqtpar;	/* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
+	uint	dqtpar;		/* 0xd146c - Doorbell Queue Tail Pointer Address Register */
+	uint	edqhpar;	/* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
+	uint	dqhpar;		/* 0xd1474 - Doorbell Queue Head Pointer Address Register */
+	char	res57[104];
+	uint	pwmr;		/* 0xd14e0 - Port-Write Mode Register */
+	uint	pwsr;		/* 0xd14e4 - Port-Write Status Register */
+	uint	epwqbar;	/* 0xd14e8 - Extended Port-Write Queue Base Address Register */
+	uint	pwqbar;		/* 0xd14ec - Port-Write Queue Base Address Register */
+	char	res58[60176];
+} ccsr_rio_t;
+
+#elif defined(FSL_RIO_IP_V2)
+
+/* RapidIO Register for IP version 2 */
+typedef struct ccsr_rio {
+	uint	didcar;		/* 0xc0000 - Device Identity Capability Register */
+	uint	dicar;		/* 0xc0004 - Device Information Capability Register */
+	uint	aidcar;		/* 0xc0008 - Assembly Identity Capability Register */
+	uint	aicar;		/* 0xc000c - Assembly Information Capability Register */
+	uint	pefcar;		/* 0xc0010 - Processing Element Features Capability Register */
+	uint	spicar;		/* 0xc0014 - Switch Port Information Capability Register */
+	uint	socar;		/* 0xc0018 - Source Operations Capability Register */
+	uint	docar;		/* 0xc001c - Destination Operations Capability Register */
+	char	res1[32];
+	uint	msr;		/* 0xc0040 - Mailbox Command And Status Register */
+	uint	pwdcsr;		/* 0xc0044 - Port-Write and Doorbell Command And Status Register */
+	char	res2[4];
+	uint	pellccsr;	/* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
+	char	res3[12];
+	uint	lcsbacsr;	/* 0xc005c - Local Configuration Space Base Address Command and Status Register */
+	uint	bdidcsr;	/* 0xc0060 - Base Device ID Command and Status Register */
+	char	res4[4];
+	uint	hbdidlcsr;	/* 0xc0068 - Host Base Device ID Lock Command and Status Register */
+	uint	ctcsr;		/* 0xc006c - Component Tag Command and Status Register */
+	char	res5[144];
+	uint	pmbh0csr;	/* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
+	char	res6[28];
+	uint	pltoccsr;	/* 0xc0120 - Port Link Time-out Control Command and Status Register */
+	uint	prtoccsr;	/* 0xc0124 - Port Response Time-out Control Command and Status Register */
+	char	res7[20];
+	uint	pgccsr;		/* 0xc013c - Port General Command and Status Register */
+	uint	plmreqcsr;	/* 0xc0140 - Port Link Maintenance Request Command and Status Register */
+	uint	plmrespcsr;	/* 0xc0144 - Port Link Maintenance Response Command and Status Register */
+	uint	plascsr;	/* 0xc0148 - Port Local Ackid Status Command and Status Register */
+	char	res8[12];
+	uint	pescsr;		/* 0xc0158 - Port Error and Status Command and Status Register */
+	uint	pccsr;		/* 0xc015c - Port Control Command and Status Register */
+	char	res9[1184];
+	uint	erbh;		/* 0xc0600 - Error Reporting Block Header Register */
+	char	res10[4];
+	uint	ltledcsr;	/* 0xc0608 - Logical/Transport layer error detect status register */
+	uint	ltleecsr;	/* 0xc060c - Logical/Transport layer error enable register */
+	char	res11[4];
+	uint	ltlaccsr;	/* 0xc0614 - Logical/Transport layer addresss capture register */
+	uint	ltldidccsr;	/* 0xc0618 - Logical/Transport layer device ID capture register */
+	uint	ltlcccsr;	/* 0xc061c - Logical/Transport layer control capture register */
+	char	res12[32];
+	uint	edcsr;	        /* 0xc0640 - Port 0 error detect status register */
+	uint	erecsr;	        /* 0xc0644 - Port 0 error rate enable status register */
+	uint	ecacsr;	        /* 0xc0648 - Port 0 error capture attributes register */
+	uint	pcseccsr0;	/* 0xc064c - Port 0 packet/control symbol error capture register 0 */
+	uint	peccsr1;	/* 0xc0650 - Port 0 error capture command and status register 1 */
+	uint	peccsr2;	/* 0xc0654 - Port 0 error capture command and status register 2 */
+	uint	peccsr3;	/* 0xc0658 - Port 0 error capture command and status register 3 */
+	char	res13[12];
+	uint	ercsr;	        /* 0xc0668 - Port 0 error rate command and status register */
+	uint	ertcsr;	        /* 0xc066C - Port 0 error rate threshold status register*/
+	char	res14[63892];
+	uint	llcr;		/* 0xd0004 - Logical Layer Configuration Register */
+	char	res15[8];
+	uint	epwisr;		/* 0xd0010 - Error / Port-Write Interrupt Status Register */
+	char	res16[12];
+	uint	lretcr;		/* 0xd0020 - Logical Retry Error Threshold Configuration Register */
+	char	res17[92];
+	uint	pretcr;		/* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
+	char	res18[124];
+	uint	adidcsr;	/* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
+	char	res19[28];
+	uint	ptaacr;	        /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
+	char	res20[12];
+	uint	iecsr;	        /* 0xd0130 - Port 0 Implementation Error Status Register */
+	char	res21[12];
+	uint	pcr;		/* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
+	char	res22[20];
+	uint	slcsr;	        /* 0xd0158 - Port 0 Serial Link Command and Status Register */
+	char	res23[4];
+	uint	sleir;	        /* 0xd0160 - Port 0 Serial Link Error Injection Register */
+	char	res24[2716];
+	uint	rowtar0;	/* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
+	uint	rowtear0;	/* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
+	char	res25[8];
+	uint	rowar0;		/* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
+	char	res26[12];
+	uint	rowtar1;	/* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
+	uint	rowtear1;	/* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
+	uint	rowbar1;	/* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
+	char	res27[4];
+	uint	rowar1;		/* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
+	uint	rows1r1;	/* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
+	uint	rows2r1;	/* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
+	uint	rows3r1;	/* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
+	uint	rowtar2;	/* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
+	uint	rowtear2;	/* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
+	uint	rowbar2;	/* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
+	char	res28[4];
+	uint	rowar2;		/* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
+	uint	rows1r2;	/* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
+	uint	rows2r2;	/* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
+	uint	rows3r2;	/* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
+	uint	rowtar3;	/* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
+	uint	rowtear3;	/* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
+	uint	rowbar3;	/* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
+	char	res29[4];
+	uint	rowar3;		/* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
+	uint	rows1r3;	/* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
+	uint	rows2r3;	/* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
+	uint	rows3r3;	/* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
+	uint	rowtar4;	/* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
+	uint	rowtear4;	/* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
+	uint	rowbar4;	/* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
+	char	res30[4];
+	uint	rowar4;		/* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
+	uint	rows1r4;	/* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
+	uint	rows2r4;	/* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
+	uint	rows3r4;	/* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
+	uint	rowtar5;	/* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
+	uint	rowtear5;	/* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
+	uint	rowbar5;	/* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
+	char	res31[4];
+	uint	rowar5;		/* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
+	uint	rows1r5;	/* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
+	uint	rows2r5;	/* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
+	uint	rows3r5;	/* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
+	uint	rowtar6;	/* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
+	uint	rowtear6;	/* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
+	uint	rowbar6;	/* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
+	char	res32[4];
+	uint	rowar6;		/* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
+	uint	rows1r6;	/* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
+	uint	rows2r6;	/* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
+	uint	rows3r6;	/* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
+	uint	rowtar7;	/* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
+	uint	rowtear7;	/* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
+	uint	rowbar7;	/* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
+	char	res33[4];
+	uint	rowar7;		/* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
+	uint	rows1r7;	/* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
+	uint	rows2r7;	/* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
+	uint	rows3r7;	/* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
+	uint	rowtar8;	/* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
+	uint	rowtear8;	/* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
+	uint	rowbar8;	/* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
+	char	res34[4];
+	uint	rowar8;		/* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
+	uint	rows1r8;	/* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
+	uint	rows2r8;	/* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
+	uint	rows3r8;	/* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
+	char	res35[64];
+	uint	riwtar4;	/* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
+	char	res35a[4];
+	uint	riwbar4;	/* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
+	char	res36[4];
+	uint	riwar4;		/* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
+	char	res37[12];
+	uint	riwtar3;	/* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
+	char	res38[4];
+	uint	riwbar3;	/* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
+	char	res39[4];
+	uint	riwar3;		/* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
+	char	res40[12];
+	uint	riwtar2;	/* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
+	char	res41[4];
+	uint	riwbar2;	/* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
+	char	res42[4];
+	uint	riwar2;		/* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
+	char	res43[12];
+	uint	riwtar1;	/* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
+	char	res44[4];
+	uint	riwbar1;	/* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
+	char	res45[4];
+	uint	riwar1;		/* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
+	char	res46[12];
+	uint	riwtar0;	/* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
+	char	res47[12];
+	uint	riwar0;		/* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
+	char	res48[12];
+	uint	pnfedr;		/* 0xd0e00 - Port Notification/Fatal Error Detect Register */
+	uint	pnfedir;	/* 0xd0e04 - Port Notification/Fatal Error Detect Register */
+	uint	pnfeier;	/* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
+	uint	pecr;		/* 0xd0e0c - Port Error Control Register */
+	uint	pepcsr0;	/* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
+	uint	pepr1;		/* 0xd0e14 - Port Error Packet Register 1 */
+	uint	pepr2;		/* 0xd0e18 - Port Error Packet Register 2 */
+	char	res49[4];
+	uint	predr;		/* 0xd0e20 - Port Recoverable Error Detect Register */
+	char	res50[4];
+	uint	pertr;		/* 0xd0e28 - Port Error Recovery Threshold Register */
+	uint	prtr;		/* 0xd0e2c - Port Retry Threshold Register */
+	char	res51[8656];
+	uint	omr;		/* 0xd3000 - Outbound Mode Register */
+	uint	osr;		/* 0xd3004 - Outbound Status Register */
+	uint	eodqtpar;	/* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
+	uint	odqtpar;	/* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
+	uint	eosar;		/* 0xd3010 - Extended Outbound Unit Source Address Register */
+	uint	osar;		/* 0xd3014 - Outbound Unit Source Address Register */
+	uint	odpr;		/* 0xd3018 - Outbound Destination Port Register */
+	uint	odatr;		/* 0xd301c - Outbound Destination Attributes Register */
+	uint	odcr;		/* 0xd3020 - Outbound Doubleword Count Register */
+	uint	eodqhpar;	/* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
+	uint	odqhpar;	/* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
+	uint	oretr;	        /* 0xd302C - Outbound Retry Error Threshold Register */
+	uint	omgr;	        /* 0xd3030 - Outbound Multicast Group Register */
+	uint	omlr;	        /* 0xd3034 - Outbound Multicast List Register */
+	char	res52[40];
+	uint	imr;		/* 0xd3060 - Outbound Mode Register */
+	uint	isr;		/* 0xd3064 - Inbound Status Register */
+	uint	eidqtpar;	/* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
+	uint	idqtpar;	/* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
+	uint	eifqhpar;	/* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
+	uint	ifqhpar;	/* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
+	uint	imirir;	        /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
+	char	res53[900];
+	uint	oddmr;		/* 0xd3400 - Outbound Doorbell Mode Register */
+	uint	oddsr;		/* 0xd3404 - Outbound Doorbell Status Register */
+	char	res54[16];
+	uint	oddpr;		/* 0xd3418 - Outbound Doorbell Destination Port Register */
+	uint	oddatr;		/* 0xd341C - Outbound Doorbell Destination Attributes Register */
+	char	res55[12];
+	uint	oddretr;	/* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
+	char	res56[48];
+	uint	idmr;		/* 0xd3460 - Inbound Doorbell Mode Register */
+	uint	idsr;		/* 0xd3464 - Inbound Doorbell Status Register */
+	uint	iedqtpar;	/* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
+	uint	iqtpar;	        /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
+	uint	iedqhpar;	/* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
+	uint	idqhpar;	/* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
+	uint	idmirir;	/* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
+	char	res57[100];
+	uint	pwmr;		/* 0xd34e0 - Port-Write Mode Register */
+	uint	pwsr;		/* 0xd34e4 - Port-Write Status Register */
+	uint	epwqbar;	/* 0xd34e8 - Extended Port-Write Queue Base Address Register */
+	uint	pwqbar;		/* 0xd34ec - Port-Write Queue Base Address Register */
+	char	res58[51984];
+} ccsr_rio_t;
+
+#endif
+#endif /* __ASM_PPC_IMMAP_FSL_RIO_H_ */
-- 
1.5.2

[U-Boot-Users] [PATCH 3/3] Add RapidIO support to MPC8641HPCN, MPC8548CDS, MPC8568MDS boards.

[Zhang Wei]

Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
---
 board/freescale/mpc8548cds/mpc8548cds.c   |    8 ++++++++
 board/freescale/mpc8568mds/mpc8568mds.c   |    9 +++++++++
 board/freescale/mpc8641hpcn/mpc8641hpcn.c |    9 +++++++++
 3 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 47e2dd8..fe0ff27 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <pci.h>
+#include <rio.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
@@ -517,6 +518,13 @@ int last_stage_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_RAPIDIO
+void rio_init_board()
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	fsl_rio_init(&immap->im_rio, 0);
+}
+#endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
 void
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 3c3726b..239cf2a 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <pci.h>
+#include <rio.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
@@ -534,6 +535,14 @@ pci_init_board(void)
 }
 #endif /* CONFIG_PCI */
 
+#ifdef CONFIG_RAPIDIO
+void rio_init_board()
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	fsl_rio_init(&immap->im_rio, 0);
+}
+#endif
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 8278789..cc7c8be 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -22,6 +22,7 @@
 
 #include <common.h>
 #include <pci.h>
+#include <rio.h>
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
 #include <asm/immap_fsl_pci.h>
@@ -321,6 +322,14 @@ void pci_init_board(void)
 
 }
 
+#ifdef CONFIG_RAPIDIO
+void rio_init_board()
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	fsl_rio_init(&immap->im_rio, 0);
+}
+#endif
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
-- 
1.5.2

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Kumar Gala]

On Jan 10, 2008, at 5:38 AM, Zhang Wei wrote:

> The patch adds the RapidIO framework into U-Boot. The board  
> configuration
> can be added into individual rio_init_board() function. Some functions
> about RapidIO can be added later.

can you explain what might get added in the future.  At this point all  
this code seems to exist to just do fsl_rio_quirk.

> The support for Freescale PowerPC RapidIO controller is also added.
>
> Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
> ---
> Makefile              |    1 +
> drivers/rio/Makefile  |   35 ++++++++++++++++++++++++++
> drivers/rio/fsl_rio.c |   64 ++++++++++++++++++++++++++++++++++++++++ 
> ++++++++
> drivers/rio/rio.c     |   65 ++++++++++++++++++++++++++++++++++++++++ 
> +++++++++
> include/common.h      |    3 ++
> include/rio.h         |   46 ++++++++++++++++++++++++++++++++++
> include/rio_ids.h     |    9 +++++++
> lib_ppc/board.c       |    5 ++++
> 8 files changed, 228 insertions(+), 0 deletions(-)
> create mode 100644 drivers/rio/Makefile
> create mode 100644 drivers/rio/fsl_rio.c
> create mode 100644 drivers/rio/rio.c
> create mode 100644 include/rio.h
> create mode 100644 include/rio_ids.h

[snip]

> diff --git a/drivers/rio/fsl_rio.c b/drivers/rio/fsl_rio.c
> new file mode 100644
> index 0000000..c8bfa92
> --- /dev/null
> +++ b/drivers/rio/fsl_rio.c
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights  
> reserved.
> + *
> + * Author: Zhang Wei, wei.zhang at freescale.com, Jan 2008
> + *
> + * Description:
> + * Freescale PowerPC RapidIO controller initialization file.
> + *
> + * This is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as  
> published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#include <common.h>
> +
> +#ifdef CONFIG_RAPIDIO

you don't need to do file protection like this anymore with the new  
build system.

>
> +#include <command.h>
> +#include <malloc.h>
> +#include <rio.h>
> +#include <rio_ids.h>
> +
> +#include <asm/processor.h>
> +#include <asm/io.h>
> +#include <asm/immap_86xx.h>
> +#include <asm/io.h>
> +
> +void fsl_rio_init(void *base, int busno)
> +{
> +	struct rio_dev *dev;
> +	volatile ccsr_rio_t *rio = base;
> +	struct rio_controller *hose;
> +
> +	dev = malloc(sizeof(struct rio_dev));
> +	memset(dev, 0, sizeof(struct rio_dev));
> +
> +	dev->vendor = in_be32(&rio->didcar) & 0xffff;
> +	dev->device = (in_be32(&rio->didcar) >> 16) & 0xffff;
> +
> +	hose = malloc(sizeof(struct rio_controller));
> +	memset(hose, 0, sizeof(struct rio_controller));
> +
> +	INIT_LIST_HEAD(&hose->dev_list);
> +	hose->busno = busno;
> +	hose->base = base;
> +	hose->self = dev;
> +	list_add_tail(&hose->node, &rio_hose_list);
> +
> +	printf("RIO%d (%04x:%04x) on 0x%08x\n", hose->busno, dev->vendor,
> +			dev->device, base);
> +}
> +
> +void fsl_rio_quirk(struct rio_controller *hose, struct rio_dev *rdev)
> +{
> +#ifdef FSL_RIO_IP_V2
> +	volatile ccsr_rio_t *rio = hose->base;
> +	/* Set the controller to accept all packets
> +	 * without checking the target ID
> +	 */
> +	out_be32(&rio->ptaacr, 1);
> +#endif
> +}
> +#endif
> diff --git a/drivers/rio/rio.c b/drivers/rio/rio.c
> new file mode 100644
> index 0000000..9391384
> --- /dev/null
> +++ b/drivers/rio/rio.c
> @@ -0,0 +1,65 @@
> +/*
> + * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights  
> reserved.
> + *
> + * Author: Zhang Wei, wei.zhang at freescale.com, Jun 2007
> + *
> + * Description:
> + * RapidIO initialization file.
> + *
> + * This is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as  
> published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#include <common.h>
> +
> +#ifdef CONFIG_RAPIDIO
> +
> +#include <command.h>
> +#include <linux/list.h>
> +#include <rio.h>
> +#include <rio_ids.h>
> +#include <asm/processor.h>
> +#include <asm/io.h>
> +
> +struct list_head rio_hose_list;
> +
> +struct rio_quirk rio_post_quirk[] = {
> +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8548E, fsl_rio_quirk},
> +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8548, fsl_rio_quirk},
> +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8568E, fsl_rio_quirk},
> +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8568, fsl_rio_quirk},
> +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8641, fsl_rio_quirk},
> +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8641D, fsl_rio_quirk},
> +	{},
> +};
> +
> +void rio_hose_post(void)
> +{
> +	struct rio_controller *hose;
> +	struct rio_quirk *post_quirk;
> +
> +	list_for_each_entry(hose, &rio_hose_list, node)
> +		for (post_quirk = rio_post_quirk;
> +		     post_quirk->vendor || post_quirk->device; post_quirk++)
> +			if ((post_quirk->vendor == hose->self->vendor)
> +				  && (post_quirk->device == hose->self->device)
> +				  && post_quirk->quirk) {
> +				post_quirk->quirk(hose, hose->self);
> +				break;
> +			}
> +}

do we really need a full blown quirk system, or can we just let the  
board code handle this?

>
> +
> +void rio_init(void)
> +{
> +	INIT_LIST_HEAD(&rio_hose_list);
> +
> +	/* Call board specific rio_init() */
> +	rio_init_board();

what's the point of this.  Why not just do this from some pre-existing  
board init function?

>
> +
> +	rio_hose_post();
> +}
> +
> +#endif /* CONFIG_RAPIDIO */

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Zhang Wei]

> 
> On Jan 10, 2008, at 5:38 AM, Zhang Wei wrote:
> 
> > The patch adds the RapidIO framework into U-Boot. The board  
> > configuration
> > can be added into individual rio_init_board() function. 
> Some functions
> > about RapidIO can be added later.
> 
> can you explain what might get added in the future.  At this 
> point all  
> this code seems to exist to just do fsl_rio_quirk.

Now only fsl_rio_quirk. We can add other jobs such as RapidIO network
enumeration in the future.

Cheers!
Wei.

> 
> > The support for Freescale PowerPC RapidIO controller is also added.
> >
> > Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
> > ---
> > Makefile              |    1 +
> > drivers/rio/Makefile  |   35 ++++++++++++++++++++++++++
> > drivers/rio/fsl_rio.c |   64 
> ++++++++++++++++++++++++++++++++++++++++ 
> > ++++++++
> > drivers/rio/rio.c     |   65 
> ++++++++++++++++++++++++++++++++++++++++ 
> > +++++++++
> > include/common.h      |    3 ++
> > include/rio.h         |   46 ++++++++++++++++++++++++++++++++++
> > include/rio_ids.h     |    9 +++++++
> > lib_ppc/board.c       |    5 ++++
> > 8 files changed, 228 insertions(+), 0 deletions(-)
> > create mode 100644 drivers/rio/Makefile
> > create mode 100644 drivers/rio/fsl_rio.c
> > create mode 100644 drivers/rio/rio.c
> > create mode 100644 include/rio.h
> > create mode 100644 include/rio_ids.h
> 
> [snip]
> 
> > diff --git a/drivers/rio/fsl_rio.c b/drivers/rio/fsl_rio.c
> > new file mode 100644
> > index 0000000..c8bfa92
> > --- /dev/null
> > +++ b/drivers/rio/fsl_rio.c
> > @@ -0,0 +1,64 @@
> > +/*
> > + * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights  
> > reserved.
> > + *
> > + * Author: Zhang Wei, wei.zhang at freescale.com, Jan 2008
> > + *
> > + * Description:
> > + * Freescale PowerPC RapidIO controller initialization file.
> > + *
> > + * This is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as  
> > published by
> > + * the Free Software Foundation; either version 2 of the 
> License, or
> > + * (at your option) any later version.
> > + *
> > + */
> > +
> > +#include <common.h>
> > +
> > +#ifdef CONFIG_RAPIDIO
> 
> you don't need to do file protection like this anymore with the new  
> build system.
> 
> >
> > +#include <command.h>
> > +#include <malloc.h>
> > +#include <rio.h>
> > +#include <rio_ids.h>
> > +
> > +#include <asm/processor.h>
> > +#include <asm/io.h>
> > +#include <asm/immap_86xx.h>
> > +#include <asm/io.h>
> > +
> > +void fsl_rio_init(void *base, int busno)
> > +{
> > +	struct rio_dev *dev;
> > +	volatile ccsr_rio_t *rio = base;
> > +	struct rio_controller *hose;
> > +
> > +	dev = malloc(sizeof(struct rio_dev));
> > +	memset(dev, 0, sizeof(struct rio_dev));
> > +
> > +	dev->vendor = in_be32(&rio->didcar) & 0xffff;
> > +	dev->device = (in_be32(&rio->didcar) >> 16) & 0xffff;
> > +
> > +	hose = malloc(sizeof(struct rio_controller));
> > +	memset(hose, 0, sizeof(struct rio_controller));
> > +
> > +	INIT_LIST_HEAD(&hose->dev_list);
> > +	hose->busno = busno;
> > +	hose->base = base;
> > +	hose->self = dev;
> > +	list_add_tail(&hose->node, &rio_hose_list);
> > +
> > +	printf("RIO%d (%04x:%04x) on 0x%08x\n", hose->busno, 
> dev->vendor,
> > +			dev->device, base);
> > +}
> > +
> > +void fsl_rio_quirk(struct rio_controller *hose, struct 
> rio_dev *rdev)
> > +{
> > +#ifdef FSL_RIO_IP_V2
> > +	volatile ccsr_rio_t *rio = hose->base;
> > +	/* Set the controller to accept all packets
> > +	 * without checking the target ID
> > +	 */
> > +	out_be32(&rio->ptaacr, 1);
> > +#endif
> > +}
> > +#endif
> > diff --git a/drivers/rio/rio.c b/drivers/rio/rio.c
> > new file mode 100644
> > index 0000000..9391384
> > --- /dev/null
> > +++ b/drivers/rio/rio.c
> > @@ -0,0 +1,65 @@
> > +/*
> > + * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. 
> All rights  
> > reserved.
> > + *
> > + * Author: Zhang Wei, wei.zhang at freescale.com, Jun 2007
> > + *
> > + * Description:
> > + * RapidIO initialization file.
> > + *
> > + * This is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as  
> > published by
> > + * the Free Software Foundation; either version 2 of the 
> License, or
> > + * (at your option) any later version.
> > + *
> > + */
> > +
> > +#include <common.h>
> > +
> > +#ifdef CONFIG_RAPIDIO
> > +
> > +#include <command.h>
> > +#include <linux/list.h>
> > +#include <rio.h>
> > +#include <rio_ids.h>
> > +#include <asm/processor.h>
> > +#include <asm/io.h>
> > +
> > +struct list_head rio_hose_list;
> > +
> > +struct rio_quirk rio_post_quirk[] = {
> > +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8548E, 
> fsl_rio_quirk},
> > +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8548, fsl_rio_quirk},
> > +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8568E, 
> fsl_rio_quirk},
> > +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8568, fsl_rio_quirk},
> > +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8641, fsl_rio_quirk},
> > +	{RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8641D, 
> fsl_rio_quirk},
> > +	{},
> > +};
> > +
> > +void rio_hose_post(void)
> > +{
> > +	struct rio_controller *hose;
> > +	struct rio_quirk *post_quirk;
> > +
> > +	list_for_each_entry(hose, &rio_hose_list, node)
> > +		for (post_quirk = rio_post_quirk;
> > +		     post_quirk->vendor || post_quirk->device; 
> post_quirk++)
> > +			if ((post_quirk->vendor == hose->self->vendor)
> > +				  && (post_quirk->device == 
> hose->self->device)
> > +				  && post_quirk->quirk) {
> > +				post_quirk->quirk(hose, hose->self);
> > +				break;
> > +			}
> > +}
> 
> do we really need a full blown quirk system, or can we just let the  
> board code handle this?
> 
> >
> > +
> > +void rio_init(void)
> > +{
> > +	INIT_LIST_HEAD(&rio_hose_list);
> > +
> > +	/* Call board specific rio_init() */
> > +	rio_init_board();
> 
> what's the point of this.  Why not just do this from some 
> pre-existing  
> board init function?
> 
> >
> > +
> > +	rio_hose_post();
> > +}
> > +
> > +#endif /* CONFIG_RAPIDIO */
> 
> 
> 
> 

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Kumar Gala]

On Jan 10, 2008, at 8:10 PM, Zhang Wei wrote:

>>
>> On Jan 10, 2008, at 5:38 AM, Zhang Wei wrote:
>>
>>> The patch adds the RapidIO framework into U-Boot. The board
>>> configuration
>>> can be added into individual rio_init_board() function.
>> Some functions
>>> about RapidIO can be added later.
>>
>> can you explain what might get added in the future.  At this
>> point all
>> this code seems to exist to just do fsl_rio_quirk.
>
> Now only fsl_rio_quirk. We can add other jobs such as RapidIO network
> enumeration in the future.

seems like a lot of code until we are at that point.

- k

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Zhang Wei]

> 
> On Jan 10, 2008, at 8:10 PM, Zhang Wei wrote:
> 
> >>
> >> On Jan 10, 2008, at 5:38 AM, Zhang Wei wrote:
> >>
> >>> The patch adds the RapidIO framework into U-Boot. The board
> >>> configuration
> >>> can be added into individual rio_init_board() function.
> >> Some functions
> >>> about RapidIO can be added later.
> >>
> >> can you explain what might get added in the future.  At this
> >> point all
> >> this code seems to exist to just do fsl_rio_quirk.
> >
> > Now only fsl_rio_quirk. We can add other jobs such as 
> RapidIO network
> > enumeration in the future.
> 
> seems like a lot of code until we are at that point.

Right, lots of work :). The roadmap also depends on kernel driver of
RapidIO.

Cheers!
Wei.

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Kumar Gala]

On Jan 10, 2008, at 11:06 PM, Zhang Wei wrote:

>>
>> On Jan 10, 2008, at 8:10 PM, Zhang Wei wrote:
>>
>>>>
>>>> On Jan 10, 2008, at 5:38 AM, Zhang Wei wrote:
>>>>
>>>>> The patch adds the RapidIO framework into U-Boot. The board
>>>>> configuration
>>>>> can be added into individual rio_init_board() function.
>>>> Some functions
>>>>> about RapidIO can be added later.
>>>>
>>>> can you explain what might get added in the future.  At this
>>>> point all
>>>> this code seems to exist to just do fsl_rio_quirk.
>>>
>>> Now only fsl_rio_quirk. We can add other jobs such as
>> RapidIO network
>>> enumeration in the future.
>>
>> seems like a lot of code until we are at that point.
>
> Right, lots of work :). The roadmap also depends on kernel driver of
> RapidIO.

Sure, I guess my point is that until there is something beyond  
fsl_rio_quirk that would use the framework I don't see why we should  
put it into u-boot.

- k

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Zhang Wei]

> 
> On Jan 10, 2008, at 11:06 PM, Zhang Wei wrote:
> 
> >>
> >> On Jan 10, 2008, at 8:10 PM, Zhang Wei wrote:
> >>
> >>>>
> >>>> On Jan 10, 2008, at 5:38 AM, Zhang Wei wrote:
> >>>>
> >>>>> The patch adds the RapidIO framework into U-Boot. The board
> >>>>> configuration
> >>>>> can be added into individual rio_init_board() function.
> >>>> Some functions
> >>>>> about RapidIO can be added later.
> >>>>
> >>>> can you explain what might get added in the future.  At this
> >>>> point all
> >>>> this code seems to exist to just do fsl_rio_quirk.
> >>>
> >>> Now only fsl_rio_quirk. We can add other jobs such as
> >> RapidIO network
> >>> enumeration in the future.
> >>
> >> seems like a lot of code until we are at that point.
> >
> > Right, lots of work :). The roadmap also depends on kernel driver of
> > RapidIO.
> 
> Sure, I guess my point is that until there is something beyond  
> fsl_rio_quirk that would use the framework I don't see why we should  
> put it into u-boot.
> 
Why we do not start the job with a formal framework?

Cheers!
Wei.

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Kumar Gala]

>>> Right, lots of work :). The roadmap also depends on kernel driver of
>>> RapidIO.
>>
>> Sure, I guess my point is that until there is something beyond
>> fsl_rio_quirk that would use the framework I don't see why we should
>> put it into u-boot.
>>
> Why we do not start the job with a formal framework?

I'll leave the decision up to Wolfgang.  Just giving my two cents  
about it.

- k

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Wolfgang Denk]

In message <5E974ACF-3EBE-405A-92AC-BFC2FD391E43@kernel.crashing.org> you wrote:
> >>> Right, lots of work :). The roadmap also depends on kernel driver of
> >>> RapidIO.
> >>
> >> Sure, I guess my point is that until there is something beyond
> >> fsl_rio_quirk that would use the framework I don't see why we should
> >> put it into u-boot.
> >>
> > Why we do not start the job with a formal framework?
> 
> I'll leave the decision up to Wolfgang.  Just giving my two cents  
> about it.

Always all difficult decisions are left up to me :-(

I'd appreciate to see a formal framework for this, but  then  I  also
think  that  this needs some generalization which may be difficult or
even impossible with the initial implementation. So  I  will  neither
protest against nor insist on such a formal framework.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Imagination is more important than knowledge.      -- Albert Einstein

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Wolfgang Denk]

In message <11999650823191-git-send-email-wei.zhang@freescale.com> you wrote:
> The patch adds the RapidIO framework into U-Boot. The board configuration
> can be added into individual rio_init_board() function. Some functions
> about RapidIO can be added later.
> 
> The support for Freescale PowerPC RapidIO controller is also added.

I'm afraid I lost track of the status of these patches while  reading
all  the discussion - is this supposed to go into this release as is,
or is there some rework going on?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If only God would give me some clear sign! Like making a large  depo-
sit in my name at a Swiss Bank.                         - Woody Allen

[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot

[Kumar Gala]

On Jan 12, 2008, at 2:11 PM, Wolfgang Denk wrote:

> In message <11999650823191-git-send-email-wei.zhang@freescale.com>  
> you wrote:
>> The patch adds the RapidIO framework into U-Boot. The board  
>> configuration
>> can be added into individual rio_init_board() function. Some  
>> functions
>> about RapidIO can be added later.
>>
>> The support for Freescale PowerPC RapidIO controller is also added.
>
> I'm afraid I lost track of the status of these patches while  reading
> all  the discussion - is this supposed to go into this release as is,
> or is there some rework going on?

I think I had a minor comment about not needing the file level #ifdef  
anymore because of the new build system.

- k