* [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
@ 2008-01-13 21:11 Matthias Fuchs
2008-01-13 22:08 ` Wolfgang Denk
0 siblings, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-13 21:11 UTC (permalink / raw)
To: u-boot
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
board/esd/du440/Makefile | 51 ++
board/esd/du440/config.mk | 41 ++
board/esd/du440/du440.c | 1171 ++++++++++++++++++++++++++++++++++++++++++++
board/esd/du440/du440.h | 42 ++
board/esd/du440/init.S | 80 +++
board/esd/du440/u-boot.lds | 145 ++++++
6 files changed, 1530 insertions(+), 0 deletions(-)
create mode 100644 board/esd/du440/Makefile
create mode 100644 board/esd/du440/config.mk
create mode 100644 board/esd/du440/du440.c
create mode 100644 board/esd/du440/du440.h
create mode 100644 board/esd/du440/init.S
create mode 100644 board/esd/du440/u-boot.lds
diff --git a/board/esd/du440/Makefile b/board/esd/du440/Makefile
new file mode 100644
index 0000000..e996a0a
--- /dev/null
+++ b/board/esd/du440/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esd/du440/config.mk b/board/esd/du440/config.mk
new file mode 100644
index 0000000..e62b8d3
--- /dev/null
+++ b/board/esd/du440/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
new file mode 100644
index 0000000..0c8d59b
--- /dev/null
+++ b/board/esd/du440/du440.c
@@ -0,0 +1,1171 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <i2c.h>
+#include <ppc440.h>
+#include "du440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern ulong flash_get_size (ulong base, int banknum);
+
+int usbhub_init(void);
+int dvi_init(void);
+int eeprom_write_enable (unsigned dev_addr, int state);
+int board_revision(void);
+
+static int du440_post_errors;
+
+int board_early_init_f(void)
+{
+ u32 sdr0_cust0;
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, 0xb8400000);
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *-------------------------------------------------------------------*/
+ out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_OSRL, 0x50055400);
+ out_be32((void*)GPIO0_OSRH, 0x550050aa);
+ out_be32((void*)GPIO0_TSRL, 0x50055400);
+ out_be32((void*)GPIO0_TSRH, 0x55005000);
+ out_be32((void*)GPIO0_ISR1L, 0x50000000);
+ out_be32((void*)GPIO0_ISR1H, 0x00000000);
+ out_be32((void*)GPIO0_ISR2L, 0x00000000);
+ out_be32((void*)GPIO0_ISR2H, 0x00000100);
+ out_be32((void*)GPIO0_ISR3L, 0x00000000);
+ out_be32((void*)GPIO0_ISR3H, 0x00000000);
+
+ out_be32((void*)GPIO1_OR, 0x00000000);
+ out_be32((void*)GPIO1_TCR, 0xc2000000 |
+ CFG_GPIO1_IORSTN |
+ CFG_GPIO1_LEDUSR1 |
+ CFG_GPIO1_LEDUSR2 |
+ CFG_GPIO1_LEDPOST |
+ CFG_GPIO1_LEDDU);
+ out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
+
+ out_be32((void*)GPIO1_OSRL, 0x5c280000);
+ out_be32((void*)GPIO1_OSRH, 0x00000000);
+ out_be32((void*)GPIO1_TSRL, 0x0c000000);
+ out_be32((void*)GPIO1_TSRH, 0x00000000);
+ out_be32((void*)GPIO1_ISR1L, 0x00005550);
+ out_be32((void*)GPIO1_ISR1H, 0x00000000);
+ out_be32((void*)GPIO1_ISR2L, 0x00050000);
+ out_be32((void*)GPIO1_ISR2H, 0x00000000);
+ out_be32((void*)GPIO1_ISR3L, 0x01400000);
+ out_be32((void*)GPIO1_ISR3H, 0x00000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ /*
+ * UIC1:
+ * bit30: ext. Irq 1: PLD : int 32+30
+ */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xfffffffd);
+ mtdcr(uic1tr, 0x00000000);
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ /*
+ * UIC2
+ * bit3: ext. Irq 2: DCF77 : int 64+3
+ */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+
+ /* setup EMAC bridge interface */
+ if (board_revision() == 0) {
+ /* 1 x MII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_1_2;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_1_2;
+ } else {
+ /* 2 x SMII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_6;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_6;
+ }
+
+ /* enable 2nd IIC */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* PCI arbiter enabled */
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg);
+
+ /* setup NAND FLASH */
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ (0x80000000 >> (28 + CFG_NAND0_CS)) |
+ (0x80000000 >> (28 + CFG_NAND1_CS));
+ mtsdr(SDR0_CUST0, sdr0_cust0);
+
+ return 0;
+}
+
+/*---------------------------------------------------------------------------+
+ | misc_init_r.
+ +---------------------------------------------------------------------------*/
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val = 0;
+ u32 reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ int i, j;
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(ebccfga, pb0cr);
+ mtdcr(ebccfgd, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /*
+ * USB suff...
+ */
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+
+ /* An 8-bit/60MHz interface is the only possible alternative
+ when connecting the Device to the PHY */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+
+ /* To enable the USB 2.0 Device function through the UTMI interface */
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /* clear resets */
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy)\n");
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
+ mtdcr(plb4_acr, reg);
+
+ /*
+ * release IO-RST#
+ * We have to wait at least 560ms until we may call usbhub_init
+ */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN);
+
+ /*
+ * flash USR1/2 LEDs (600ms)
+ * This results in the necessary delay from IORST# until
+ * calling usbhub_init will succeed
+ */
+ for (j = 0; j < 3; j++) {
+ out_be32((void*)GPIO1_OR,
+ (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR2) |
+ CFG_GPIO1_LEDUSR1);
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+
+ out_be32((void*)GPIO1_OR,
+ (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR1) |
+ CFG_GPIO1_LEDUSR2);
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+ }
+
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
+ ~(CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2));
+
+ if (usbhub_init())
+ du440_post_errors++;
+
+ if(dvi_init())
+ du440_post_errors++;
+
+ return 0;
+}
+
+int pld_revision(void)
+{
+ out8(CFG_CPLD_BASE, 0x00);
+ return (int)(in8(CFG_CPLD_BASE) & CPLD_VERSION_MASK);
+}
+
+int board_revision(void)
+{
+ int rpins = (int)((in_be32((void*)GPIO1_IR) & CFG_GPIO1_HWVER_MASK)
+ >> CFG_GPIO1_HWVER_SHIFT);
+
+ return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
+ ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
+}
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void board_show_activity (ulong timestamp)
+{
+ if ((timestamp % 100) == 0)
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) ^ CFG_GPIO1_LEDUSR1);
+}
+
+void show_activity(int arg)
+{
+}
+#endif /* CONFIG_SHOW_ACTIVITY */
+
+int du440_phy_addr(int devnum)
+{
+ if (board_revision() == 0)
+ return devnum;
+
+ return devnum + 1;
+}
+
+int checkboard(void)
+{
+ char serno[32];
+
+ puts("Board: DU440");
+
+ if (getenv_r("serial#", serno, sizeof(serno)) > 0) {
+ puts(", serial# ");
+ puts(serno);
+ }
+
+ printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
+ board_revision(), pld_revision());
+ return (0);
+}
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long addr;
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*-------------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*--------------------------------------------------------------------------+
+ * Set up Direct MMIO registers
+ *--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ | PowerPC440EPX PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +--------------------------------------------------------------------------*/
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*--------------------------------------------------------------------------+
+ * Set up Configuration registers
+ *--------------------------------------------------------------------------*/
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ PCI_VENDOR_ID_ESDGMBH);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
+
+ pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*---------------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------------*/
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* always configured as host. */
+ return (1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+int last_stage_init(void)
+{
+ int e, i;
+ /* everyting is ok: turn on POST-LED */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+
+ /* slowly blink on errors and finally keep LED off */
+ for (e = 0; e < du440_post_errors; e++) {
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDPOST);
+
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_I2C_MULTI_BUS)
+/*
+ * read field strength from I2C ADC
+ */
+int dcf77_status(void)
+{
+ unsigned int oldbus;
+ uchar u[2];
+ int U;
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(1);
+
+ if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
+ I2C_SET_BUS(oldbus);
+ return -1;
+ }
+
+ U = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
+
+ I2C_SET_BUS(oldbus);
+ return U;
+}
+
+int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int U;
+ u32 pin, pinold;
+ unsigned long long t1, t2;
+ bd_t *bd = gd->bd;
+
+ printf("DCF77: ");
+ U = dcf77_status();
+ if (U > 0)
+ printf("signal=%d mV\n", U);
+ else
+ printf("ERROR - no signal\n");
+
+#if 1
+ t1 = t2 = 0;
+ pinold = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+ while (!ctrlc()) {
+ pin = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+ if (pin && !pinold) { /* bit start */
+ t1 = get_ticks();
+ if (t2 && ((unsigned int)(t1 - t2) /
+ (bd->bi_procfreq / 1000) >= 1800))
+ printf("Start of minute\n");
+
+ t2 = t1;
+ }
+ if (t1 && !pin && pinold) { /* bit end */
+ printf("%5d\n", (unsigned int)(get_ticks() - t1) /
+ (bd->bi_procfreq / 1000));
+ }
+ pinold = pin;
+ }
+#endif
+
+ printf("Abort\n");
+ return 0;
+}
+U_BOOT_CMD(
+ dcf77, 1, 1, do_dcf77,
+ "dcf77 - Check DCF77 receiver\n",
+ NULL
+ );
+
+/*
+ * initialize USB hub via I2C1
+ */
+int usbhub_init(void)
+{
+ int reg;
+ int ret = 0;
+ unsigned int oldbus;
+ uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
+ 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
+ 0x32};
+
+ uchar stcd;
+
+ printf("Hub: ");
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(1);
+
+ for (reg = 0; reg < sizeof(u); reg++)
+ if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
+ ret = -1;
+ break;
+ }
+
+ if (ret == 0) {
+ stcd = 0x03;
+ if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
+ ret = -1;
+ }
+
+ if (ret == 0)
+ printf("initialized\n");
+ else
+ printf("failed - cannot initialize USB hub\n");
+
+ I2C_SET_BUS(oldbus);
+ return ret;
+}
+
+int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ usbhub_init();
+ return 0;
+}
+U_BOOT_CMD(
+ hubinit, 1, 1, do_hubinit,
+ "hubinit - Initialize USB hub\n",
+ NULL
+ );
+#endif /* CONFIG_I2C_MULTI_BUS */
+
+#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int boot_eeprom_write (unsigned dev_addr,
+ unsigned offset,
+ uchar *buffer,
+ unsigned cnt)
+{
+ unsigned end = offset + cnt;
+ unsigned blk_off;
+ int rcode = 0;
+
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 1);
+#endif
+ /* Write data until done or would cross a write page boundary.
+ * We must write the address again when changing pages
+ * because the address counter only increments within a page.
+ */
+
+ while (offset < end) {
+ unsigned alen, len;
+ unsigned maxlen;
+
+ uchar addr[2];
+
+ blk_off = offset & 0xFF; /* block offset */
+
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
+ addr[0] |= dev_addr; /* insert device address */
+
+ len = end - offset;
+
+ /*
+ * For a FRAM device there is no limit on the number of the
+ * bytes that can be ccessed with the single read or write
+ * operation.
+ */
+#if defined(CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+
+#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+ maxlen = BOOT_EEPROM_PAGE_SIZE -
+ BOOT_EEPROM_PAGE_OFFSET(blk_off);
+#else
+ maxlen = 0x100 - blk_off;
+#endif
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
+
+ if (len > maxlen)
+ len = maxlen;
+
+ if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
+ rcode = 1;
+
+ buffer += len;
+ offset += len;
+
+#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+ }
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 0);
+#endif
+ return rcode;
+}
+
+int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong sdsdp[4];
+
+ if (argc > 1) {
+ if (!strcmp(argv[1], "533")) {
+ printf("Bootstrapping for 533MHz\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+ sdsdp[1] = 0x095fa030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "533-66")) {
+ printf("Bootstrapping for 533MHz (66MHz PCI)\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
+ sdsdp[1] = 0x0957a030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "667")) {
+ printf("Bootstrapping for 667MHz\n");
+ sdsdp[0] = 0x8778a256;
+ /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
+ sdsdp[1] = 0x0947a030;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
+ * -> not working when overclocking 533MHz chips
+ * -> untested on 667MHz chips */
+ /* sdsdp[1]=0x095fa030; */
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ }
+ } else {
+ printf("Bootstrapping for 533MHz (default)\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+ sdsdp[1] = 0x095fa030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ }
+
+ printf("Writing boot EEPROM ...\n");
+ if (boot_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
+ 0, (uchar*)sdsdp, 16) != 0)
+ printf("boot_eeprom_write failed\n");
+ else
+ printf("done (dump via 'i2c md 52 0.1 10')\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ sbe, 2, 0, do_setup_boot_eeprom,
+ "sbe - setup boot eeprom\n",
+ NULL
+ );
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
+ (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr))
+ return -1;
+ else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CFG_GPIO0_EP_EEP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CFG_GPIO0_EP_EEP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void*)GPIO0_OR) &
+ CFG_GPIO0_EP_EEP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0)
+ puts ("Query of write access state failed.\n");
+ else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0)
+ puts ("Setup of write access state failed.\n");
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+
+static int got_pldirq;
+
+static int pld_interrupt(u32 arg)
+{
+ int rc = -1; /* not for us */
+ u8 status = in8(CFG_CPLD_BASE);
+
+ /* check for PLD interrupt */
+ if (status & PWR_INT_FLAG) {
+ /* reset this int */
+ out8(CFG_CPLD_BASE, 0);
+ rc = 0;
+ got_pldirq = 1; /* trigger backend */
+ }
+
+ return rc;
+}
+
+
+int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ got_pldirq = 0;
+
+ /* clear any pending interrupt */
+ out8(CFG_CPLD_BASE, 0);
+
+ irq_install_handler(CPLD_IRQ,
+ (interrupt_handler_t *)pld_interrupt, 0);
+
+ printf("Waiting ...\n");
+ while(!got_pldirq) {
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ break;
+ }
+ }
+ if (got_pldirq) {
+ printf("Got interrupt!\n");
+ printf("Power %sready!\n",
+ in8(CFG_CPLD_BASE) & PWR_RDY ? "":"NOT ");
+ }
+
+ irq_free_handler(CPLD_IRQ);
+ return 0;
+}
+U_BOOT_CMD(
+ wpi, 1, 1, do_waitpwrirq,
+ "wpi - Wait for power change interrupt\n",
+ NULL
+ );
+
+
+/*
+ * initialize DVI panellink transmitter
+ */
+int dvi_init(void)
+{
+ int i;
+ int ret = 0;
+ unsigned int oldbus;
+ uchar u[] = {0x08, 0x34,
+ 0x09, 0x20,
+ 0x0a, 0x90,
+ 0x0c, 0x89,
+ 0x08, 0x35};
+
+ printf("DVI: ");
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(0);
+
+ for (i = 0; i < sizeof(u); i += 2)
+ if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
+ ret = -1;
+ break;
+ }
+
+ if (ret == 0)
+ printf("initialized\n");
+ else
+ printf("failed - cannot initialize DVI transmitter\n");
+
+ I2C_SET_BUS(oldbus);
+ return ret;
+}
+
+int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ dvi_init();
+ return 0;
+}
+U_BOOT_CMD(
+ dviinit, 1, 1, do_dviinit,
+ "dviinit - Initialize DVI Panellink transmitter\n",
+ NULL
+ );
+
+
+#if 1
+/*
+ * TODO: 'time' command might be useful for others as well.
+ * Move to 'common' directory.
+ */
+int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long long start, end;
+ char c, cmd[CFG_CBSIZE];
+ char *p, *d = cmd;
+ int ret, i;
+ ulong us;
+
+ for (i = 1; i < argc; i++) {
+ p = argv[i];
+
+ if (i > 1)
+ *d++ = ' ';
+
+ while ((c = *p++) != '\0') {
+ *d++ = c;
+ }
+ }
+ *d = '\0';
+
+ start = get_ticks();
+ ret = run_command (cmd, 0);
+ end = get_ticks();
+
+ printf("ticks=%d\n", (ulong)(end - start));
+ us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
+ printf("usec=%d\n", us);
+
+ return ret;
+}
+U_BOOT_CMD(
+ time, CFG_MAXARGS, 1, do_time,
+ "time - run command and output execution time\n",
+ NULL
+ );
+#endif
+
+extern void video_hw_rectfill (
+ unsigned int bpp, /* bytes per pixel */
+ unsigned int dst_x, /* dest pos x */
+ unsigned int dst_y, /* dest pos y */
+ unsigned int dim_x, /* frame width */
+ unsigned int dim_y, /* frame height */
+ unsigned int color /* fill color */
+ );
+
+#if 0
+/*
+ * test commands for SM722 2D acceleration
+ */
+extern void video_hw_bitblt (
+ unsigned int bpp, /* bytes per pixel */
+ unsigned int src_x, /* source pos x */
+ unsigned int src_y, /* source pos y */
+ unsigned int dst_x, /* dest pos x */
+ unsigned int dst_y, /* dest pos y */
+ unsigned int dim_x, /* frame width */
+ unsigned int dim_y /* frame height */
+ );
+
+extern void video_hw_drawline (
+ unsigned int bpp,
+ unsigned int x1,
+ unsigned int y1,
+ unsigned int x2,
+ unsigned int y2,
+ unsigned int color
+ );
+
+int do_gfxfill(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int color = 0x0000f800;
+ unsigned int x=0, y=0, dx=100, dy=100;
+
+ if (argc > 1)
+ color = simple_strtoul (argv[1], NULL, 16);
+
+ if (argc > 2)
+ x = simple_strtoul (argv[2], NULL, 10);
+
+ if (argc > 3)
+ y = simple_strtoul (argv[3], NULL, 10);
+
+ if (argc > 4)
+ dx = simple_strtoul (argv[4], NULL, 10);
+
+ if (argc > 5)
+ dy = simple_strtoul (argv[5], NULL, 10);
+
+ video_hw_rectfill(2, x, y, dx, dy, color);
+
+ return 0;
+}
+U_BOOT_CMD(
+ gfxfill, CFG_MAXARGS, 1, do_gfxfill,
+ "gfxfill - fill rect\n",
+ "[color] [x] [y] [dx] [dy]\n"
+ );
+
+int do_gfxblt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int x=0, y=0, xd=500, yd=500, dx=100, dy=100;
+
+ if (argc > 1)
+ x = simple_strtoul (argv[1], NULL, 10);
+
+ if (argc > 2)
+ y = simple_strtoul (argv[2], NULL, 10);
+
+ if (argc > 3)
+ xd = simple_strtoul (argv[3], NULL, 10);
+
+ if (argc > 4)
+ yd = simple_strtoul (argv[4], NULL, 10);
+
+ if (argc > 5)
+ dx = simple_strtoul (argv[5], NULL, 10);
+
+ if (argc > 6)
+ dy = simple_strtoul (argv[6], NULL, 10);
+
+ video_hw_bitblt(2, x, y, xd, yd, dx, dy);
+
+ return 0;
+}
+U_BOOT_CMD(
+ gfxblt, CFG_MAXARGS, 1, do_gfxblt,
+ "gfxblt - bit blit\n",
+ "[x] [y] [xd] [yd] [dx] [dy]\n"
+ );
+
+
+int do_gfxline(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int color = 0x0000001f;
+ unsigned int x1=0, y1=0, x2=100, y2=100;
+
+ if (argc > 1)
+ color = simple_strtoul (argv[1], NULL, 16);
+
+ if (argc > 2)
+ x1 = simple_strtoul (argv[2], NULL, 10);
+
+ if (argc > 3)
+ y1 = simple_strtoul (argv[3], NULL, 10);
+
+ if (argc > 4)
+ x2 = simple_strtoul (argv[4], NULL, 10);
+
+ if (argc > 5)
+ y2 = simple_strtoul (argv[5], NULL, 10);
+
+ video_hw_drawline(2, x1, y1, x2, y2, color);
+
+ return 0;
+}
+U_BOOT_CMD(
+ gfxline, CFG_MAXARGS, 1, do_gfxline,
+ "gfxline - draw line\n",
+ "[color] [x1] [y1] [x2] [y2]\n"
+ );
+#endif
+
+/*
+ * graphics demo
+ * draw rectangles using pseudorandom number generator
+ * (see http://www.embedded.com/columns/technicalinsights/20900500)
+ */
+unsigned int rprime = 9972;
+static unsigned int r;
+static unsigned int Y;
+
+unsigned int prng(unsigned int max)
+{
+ if (r == 0 || r == 1 || r == -1)
+ r = rprime; /* keep from getting stuck */
+
+ r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
+ Y = (r >> 16) % max; /* choose upper bits and reduce */
+ return Y;
+}
+
+int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int color;
+ unsigned int x, y, dx, dy;
+
+ while (!ctrlc()) {
+ x = prng(1280 - 1);
+ y = prng(1024 - 1);
+ dx = prng(1280- x - 1);
+ dy = prng(1024 - y - 1);
+ color = prng(0x10000);
+ video_hw_rectfill(2, x, y, dx, dy, color);
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ gfxdemo, CFG_MAXARGS, 1, do_gfxdemo,
+ "gfxdemo - demo\n",
+ NULL
+ );
diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h
new file mode 100644
index 0000000..5c362e4
--- /dev/null
+++ b/board/esd/du440/du440.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDR0_USB0 0x0320 /* USB Control Register */
+
+#define CFG_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
+#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
+
+#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
+
+#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
+#define CFG_GPIO1_HWVER_SHIFT 4
+#define CFG_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
+#define CFG_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
+#define CFG_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
+#define CFG_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
+
+#define CPLD_VERSION_MASK 0x0f
+#define PWR_INT_FLAG 0x80
+#define PWR_RDY 0x10
+
+#define CPLD_IRQ (32+30)
+
+#define PCI_VENDOR_ID_ESDGMBH 0x12fe
+#define PCI_DEVICE_ID_DU440 0x0444
diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
new file mode 100644
index 0000000..1e15e72
--- /dev/null
+++ b/board/esd/du440/init.S
@@ -0,0 +1,80 @@
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm-ppc/mmu.h>
+#include <config.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entry for PCI IO */
+ tlbentry( CFG_PCI_IOBASE, SZ_64K, CFG_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entries for EBC: CPLD, DUMEM, DUIO */
+ tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_DUMEM_BASE, SZ_1M, CFG_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_DUIO_BASE, SZ_64K, CFG_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for NAND */
+ tlbentry( CFG_NAND0_ADDR, SZ_1K, CFG_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_NAND1_ADDR, SZ_1K, CFG_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /* TLB-entry PCI registers */
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ tlbtab_end
diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds
new file mode 100644
index 0000000..a423f98
--- /dev/null
+++ b/board/esd/du440/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
--
1.5.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
2008-01-13 21:11 [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support Matthias Fuchs
@ 2008-01-13 22:08 ` Wolfgang Denk
2008-01-14 8:58 ` Matthias Fuchs
` (2 more replies)
0 siblings, 3 replies; 24+ messages in thread
From: Wolfgang Denk @ 2008-01-13 22:08 UTC (permalink / raw)
To: u-boot
In message <200801132211.13931.matthias.fuchs@esd-electronics.com> you wrote:
> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
> ---
> board/esd/du440/Makefile | 51 ++
> board/esd/du440/config.mk | 41 ++
> board/esd/du440/du440.c | 1171 ++++++++++++++++++++++++++++++++++++++++++++
> board/esd/du440/du440.h | 42 ++
> board/esd/du440/init.S | 80 +++
> board/esd/du440/u-boot.lds | 145 ++++++
> 6 files changed, 1530 insertions(+), 0 deletions(-)
> create mode 100644 board/esd/du440/Makefile
> create mode 100644 board/esd/du440/config.mk
> create mode 100644 board/esd/du440/du440.c
> create mode 100644 board/esd/du440/du440.h
> create mode 100644 board/esd/du440/init.S
> create mode 100644 board/esd/du440/u-boot.lds
...
> diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
> new file mode 100644
> index 0000000..0c8d59b
> --- /dev/null
> +++ b/board/esd/du440/du440.c
...
> + switch (gd->bd->bi_flashsize) {
> + case 1 << 20:
> + size_val = 0;
> + break;
> + case 2 << 20:
> + size_val = 1;
> + break;
> + case 4 << 20:
> + size_val = 2;
> + break;
> + case 8 << 20:
> + size_val = 3;
> + break;
> + case 16 << 20:
> + size_val = 4;
> + break;
> + case 32 << 20:
> + size_val = 5;
> + break;
> + case 64 << 20:
> + size_val = 6;
> + break;
> + case 128 << 20:
> + size_val = 7;
> + break;
> + }
Ummm...
#include <asm/bitops.h>
...
size_val = ffs(gd->bd->bi_flashsize) - 21;
seems more straigtforward to me...
...
> + /*--------------------------------------------------------------------------+
> + | PowerPC440EPX PCI Master configuration.
> + | Map one 1Gig range of PLB/processor addresses to PCI memory space.
> + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
> + | Use byte reversed out routines to handle endianess.
> + | Make this region non-prefetchable.
> + +--------------------------------------------------------------------------*/
Here and elsewhere: this is not the requested style for multiline
comments.
> + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
> + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
> + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
> + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
> + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
> +
> + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
> + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
> + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
> + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
> + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
Please mind the maximum line length!
> + /* Write data until done or would cross a write page boundary.
> + * We must write the address again when changing pages
> + * because the address counter only increments within a page.
> + */
Please:
/*
* Write data until...
> +U_BOOT_CMD(
> + dviinit, 1, 1, do_dviinit,
> + "dviinit - Initialize DVI Panellink transmitter\n",
> + NULL
> + );
> +
> +
> +#if 1
Please remove the '#if 1' as it's redundant.
...
> +#if 0
> +/*
> + * test commands for SM722 2D acceleration
> + */
...
> +U_BOOT_CMD(
> + gfxline, CFG_MAXARGS, 1, do_gfxline,
> + "gfxline - draw line\n",
> + "[color] [x1] [y1] [x2] [y2]\n"
> + );
> +#endif
Please remove the dead code.
> diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
> new file mode 100644
> index 0000000..1e15e72
> --- /dev/null
> +++ b/board/esd/du440/init.S
> @@ -0,0 +1,80 @@
> +/*
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
Copyright missing.
You probably may want to adjust the (C) messages in some other files,
too.
> diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds
> new file mode 100644
> index 0000000..a423f98
> --- /dev/null
> +++ b/board/esd/du440/u-boot.lds
...
> + __bss_start = .;
> + .bss :
NOLOAD attribute missing. Please fix.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Crash programs fail because they are based on the theory that, with
nine women pregnant, you can get a baby a month. - Wernher von Braun
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
2008-01-13 22:08 ` Wolfgang Denk
@ 2008-01-14 8:58 ` Matthias Fuchs
2008-01-14 9:45 ` Wolfgang Denk
2008-01-16 10:47 ` [U-Boot-Users] [PATCH V2] " Matthias Fuchs
2008-01-16 10:47 ` [U-Boot-Users] [PATCH V2] ppc4xx: Complete " Matthias Fuchs
2 siblings, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-14 8:58 UTC (permalink / raw)
To: u-boot
Hi Wolfgang,
as you might have noticed the DU440 board is havily based on seuqoia code.
Nearly all of your comments apply to that board as well. I thought of the
sequoia code as exemplary reference code. And I prefer not to reformat comments
when copy and pasting from one board to another.
But if you really insist of these changes I will change the patch.
On Sunday 13 January 2008 23:08, Wolfgang Denk wrote:
>
> Ummm...
>
> #include <asm/bitops.h>
> ...
> size_val = ffs(gd->bd->bi_flashsize) - 21;
>
> seems more straigtforward to me...
>
Good idea. Thanks.
> > +#if 1
>
> Please remove the '#if 1' as it's redundant.
Ack.
>
> ...
> > +#if 0
> > +/*
> > + * test commands for SM722 2D acceleration
> > + */
> ...
> > +U_BOOT_CMD(
> > + gfxline, CFG_MAXARGS, 1, do_gfxline,
> > + "gfxline - draw line\n",
> > + "[color] [x1] [y1] [x2] [y2]\n"
> > + );
> > +#endif
>
> Please remove the dead code.
Please not. The DU440 board will get an updated smi_lynxem driver with support for the
SM722 soon. My current hack is to dirty for submission and I just got some more register
dumps from SM to support more videomodes. I will need this commented out code to test it.
I plan to remove it later.
>
>
> > diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
> > new file mode 100644
> > index 0000000..1e15e72
> > --- /dev/null
> > +++ b/board/esd/du440/init.S
> > @@ -0,0 +1,80 @@
> > +/*
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
>
> Copyright missing.
>
> You probably may want to adjust the (C) messages in some other files,
> too.
Ack. May I put my name on it? The source of this code has no copyright either.
>
> > diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds
> > new file mode 100644
> > index 0000000..a423f98
> > --- /dev/null
> > +++ b/board/esd/du440/u-boot.lds
> ...
> > + __bss_start = .;
> > + .bss :
>
> NOLOAD attribute missing. Please fix.
This is new to me. But I just noticed that all other boards have been updated according to this. So will I.
I will update my patches. Perhaps you can comment on my comments above.
Matthias
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
2008-01-14 8:58 ` Matthias Fuchs
@ 2008-01-14 9:45 ` Wolfgang Denk
2008-01-14 10:05 ` Matthias Fuchs
0 siblings, 1 reply; 24+ messages in thread
From: Wolfgang Denk @ 2008-01-14 9:45 UTC (permalink / raw)
To: u-boot
Dear Matthias,
in message <200801140958.46911.matthias.fuchs@esd-electronics.com> you wrote:
>
> as you might have noticed the DU440 board is havily based on seuqoia code.
No, I wasn't aware of this.
> Nearly all of your comments apply to that board as well. I thought of the
> sequoia code as exemplary reference code. And I prefer not to reformat comments
> when copy and pasting from one board to another.
Hm. So I have to talk with the maintainer of this board - especially
how he managed to run this through the custodian without public
review. Stefan, how did he bribe you? :-)
> But if you really insist of these changes I will change the patch.
Please do. Ideally, please include the Sequoia in your cleanup, too.
> > > +#if 0
> > > +/*
> > > + * test commands for SM722 2D acceleration
> > > + */
> > ...
> > > +U_BOOT_CMD(
> > > + gfxline, CFG_MAXARGS, 1, do_gfxline,
> > > + "gfxline - draw line\n",
> > > + "[color] [x1] [y1] [x2] [y2]\n"
> > > + );
> > > +#endif
> >
> > Please remove the dead code.
> Please not. The DU440 board will get an updated smi_lynxem driver with support for the
> SM722 soon. My current hack is to dirty for submission and I just got some more register
> dumps from SM to support more videomodes. I will need this commented out code to test it.
> I plan to remove it later.
Please remove it. We use source code management systems to maintain
test code etc. If it's "#if 0" is has no place in the public code.
> > You probably may want to adjust the (C) messages in some other files,
> > too.
> Ack. May I put my name on it? The source of this code has no copyright either.
Stefan???
> > > + __bss_start = .;
> > > + .bss :
> >
> > NOLOAD attribute missing. Please fix.
> This is new to me. But I just noticed that all other boards have been updated according to this. So will I.
Thanks.
> I will update my patches. Perhaps you can comment on my comments above.
Done :-)
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Ernest asks Frank how long he has been working for the company.
"Ever since they threatened to fire me."
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
2008-01-14 9:45 ` Wolfgang Denk
@ 2008-01-14 10:05 ` Matthias Fuchs
2008-01-14 10:35 ` Stefan Roese
0 siblings, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-14 10:05 UTC (permalink / raw)
To: u-boot
I will update the DU440 patch tonight and also update the sequoia
sources in the same manner. So Stefan can lean back :-)
Matthias
On Monday 14 January 2008 10:45, Wolfgang Denk wrote:
> Dear Matthias,
>
> in message <200801140958.46911.matthias.fuchs@esd-electronics.com> you wrote:
> >
> > as you might have noticed the DU440 board is havily based on seuqoia code.
>
> No, I wasn't aware of this.
>
> > Nearly all of your comments apply to that board as well. I thought of the
> > sequoia code as exemplary reference code. And I prefer not to reformat comments
> > when copy and pasting from one board to another.
>
> Hm. So I have to talk with the maintainer of this board - especially
> how he managed to run this through the custodian without public
> review. Stefan, how did he bribe you? :-)
>
> > But if you really insist of these changes I will change the patch.
>
> Please do. Ideally, please include the Sequoia in your cleanup, too.
>
> > > > +#if 0
> > > > +/*
> > > > + * test commands for SM722 2D acceleration
> > > > + */
> > > ...
> > > > +U_BOOT_CMD(
> > > > + gfxline, CFG_MAXARGS, 1, do_gfxline,
> > > > + "gfxline - draw line\n",
> > > > + "[color] [x1] [y1] [x2] [y2]\n"
> > > > + );
> > > > +#endif
> > >
> > > Please remove the dead code.
> > Please not. The DU440 board will get an updated smi_lynxem driver with support for the
> > SM722 soon. My current hack is to dirty for submission and I just got some more register
> > dumps from SM to support more videomodes. I will need this commented out code to test it.
> > I plan to remove it later.
>
> Please remove it. We use source code management systems to maintain
> test code etc. If it's "#if 0" is has no place in the public code.
>
> > > You probably may want to adjust the (C) messages in some other files,
> > > too.
> > Ack. May I put my name on it? The source of this code has no copyright either.
>
> Stefan???
>
> > > > + __bss_start = .;
> > > > + .bss :
> > >
> > > NOLOAD attribute missing. Please fix.
> > This is new to me. But I just noticed that all other boards have been updated according to this. So will I.
>
> Thanks.
>
> > I will update my patches. Perhaps you can comment on my comments above.
>
> Done :-)
>
> Best regards,
>
> Wolfgang Denk
>
--
-------------------------------------------------------------------------
Dipl.-Ing. Matthias Fuchs
SD4
esd electronic system design gmbh
Vahrenwalder Str. 207 - 30165 Hannover - GERMANY
Telefon: 0511-37298-0 - Fax: 0511-37298-68
Bitte besuchen Sie uns im Internet unter http://www.esd.eu
Quality Products - Made in Germany
-------------------------------------------------------------------------
Gesch?ftsf?hrer: Klaus Detering, Dr. Werner Schulze
Amtsgericht Hannover HRB 51373 - VAT-ID DE 115672832
-------------------------------------------------------------------------
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
2008-01-14 10:05 ` Matthias Fuchs
@ 2008-01-14 10:35 ` Stefan Roese
2008-01-15 22:17 ` [U-Boot-Users] [PATCH] ppc4xx: Sequoia coding style cleanup and beautification Matthias Fuchs
2008-01-16 12:05 ` [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support Matthias Fuchs
0 siblings, 2 replies; 24+ messages in thread
From: Stefan Roese @ 2008-01-14 10:35 UTC (permalink / raw)
To: u-boot
On Monday 14 January 2008, Matthias Fuchs wrote:
> I will update the DU440 patch tonight and also update the sequoia
> sources in the same manner. So Stefan can lean back :-)
/me leans back and keeps busy with other high priority stuff. :)
Thanks Matthias!
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH] ppc4xx: Sequoia coding style cleanup and beautification
2008-01-14 10:35 ` Stefan Roese
@ 2008-01-15 22:17 ` Matthias Fuchs
2008-01-16 7:31 ` Stefan Roese
2008-01-16 12:05 ` [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support Matthias Fuchs
1 sibling, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-15 22:17 UTC (permalink / raw)
To: u-boot
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
board/amcc/sequoia/init.S | 7 +-
board/amcc/sequoia/sequoia.c | 256 ++++++++++++++++++++----------------------
2 files changed, 124 insertions(+), 139 deletions(-)
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index ff6ae66..563f518 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -1,4 +1,6 @@
/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr at denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,7 +25,7 @@
#include <asm-ppc/mmu.h>
#include <config.h>
-/**************************************************************************
+/*
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
@@ -31,8 +33,7 @@
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
- *
- *************************************************************************/
+ */
.section .bootpg,"ax"
.globl tlbtab
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index e46efef..0cccfd2 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -4,7 +4,7 @@
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol at fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel at fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel at fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -29,11 +29,12 @@
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/bitops.h>
#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
ulong flash_get_size (ulong base, int banknum);
@@ -46,9 +47,9 @@ int board_early_init_f(void)
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
- /*--------------------------------------------------------------------
+ /*
* Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
+ */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
@@ -87,9 +88,11 @@ int board_early_init_f(void)
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_4;
mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_4;
mtsdr(SDR0_PFC2, sdr0_pfc2);
mtsdr(SDR0_PFC1, sdr0_pfc1);
@@ -109,9 +112,7 @@ int board_early_init_f(void)
return 0;
}
-/*---------------------------------------------------------------------------+
- | misc_init_r.
- +---------------------------------------------------------------------------*/
+
int misc_init_r(void)
{
uint pbcr;
@@ -124,11 +125,7 @@ int misc_init_r(void)
char *act = getenv("usbact");
#endif
- /*
- * FLASH stuff...
- */
-
- /* Re-do sizing to get full correct info */
+ /* Re-do flash sizing to get full correct info */
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@@ -140,32 +137,7 @@ int misc_init_r(void)
mtdcr(ebccfga, pb0cr);
#endif
pbcr = mfdcr(ebccfgd);
- switch (gd->bd->bi_flashsize) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- case 32 << 20:
- size_val = 5;
- break;
- case 64 << 20:
- size_val = 6;
- break;
- case 128 << 20:
- size_val = 7;
- break;
- }
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(ebccfga, pb3cr);
@@ -197,7 +169,7 @@ int misc_init_r(void)
* USB suff...
*/
#ifdef CONFIG_440EPX
- if (act == NULL || strcmp(act, "hostdev") == 0) {
+ if (act == NULL || strcmp(act, "hostdev") == 0) {
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB2D0CR, usb2d0cr);
@@ -205,27 +177,32 @@ int misc_init_r(void)
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
- /* An 8-bit/60MHz interface is the only possible alternative
- when connecting the Device to the PHY */
+ /*
+ * An 8-bit/60MHz interface is the only possible alternative
+ * when connecting the Device to the PHY
+ */
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
- /* To enable the USB 2.0 Device function through the UTMI interface */
+ /*
+ * To enable the USB 2.0 Device function
+ * through the UTMI interface
+ */
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
@@ -245,13 +222,13 @@ int misc_init_r(void)
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
udelay (1000);
@@ -276,31 +253,31 @@ int misc_init_r(void)
mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1);
- /*clear resets*/
+ /* clear resets */
udelay (1000);
mtsdr(SDR0_SRST1, 0x00000000);
udelay (1000);
@@ -325,6 +302,7 @@ int misc_init_r(void)
return 0;
}
+
int checkboard(void)
{
char *s = getenv("serial#");
@@ -350,6 +328,7 @@ int checkboard(void)
return (0);
}
+
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
@@ -388,6 +367,7 @@ int testdram(void)
}
#endif
+
#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
/*
* Assign interrupts to PCI devices.
@@ -398,43 +378,43 @@ void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
}
#endif
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
+
+/*
+ * pci_pre_init
*
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
*
- ************************************************************************/
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB3 devices to 0.
- | Set PLB3 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
+ /*
+ * Set priority for all PLB3 devices to 0.
+ * Set PLB3 arbiter to fair mode.
+ */
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB4 devices to 0.
- +-------------------------------------------------------------------------*/
+ /*
+ * Set priority for all PLB4 devices to 0.
+ */
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
- /*-------------------------------------------------------------------------+
- | Set Nebula PLB4 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
+ /*
+ * Set Nebula PLB4 arbiter to fair mode.
+ */
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
@@ -456,47 +436,52 @@ int pci_pre_init(struct pci_controller *hose)
}
#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
+
+/*
+ * pci_target_init
*
- ************************************************************************/
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
- /*--------------------------------------------------------------------------+
+ /*
* Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440EPX PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ */
+ /*
+ * PowerPC440EPX PCI Master configuration.
+ * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ * PLB address 0xA0000000-0xDFFFFFFF
+ * ==> PCI address 0xA0000000-0xDFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ * Make this region non-prefetchable.
+ */
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
+ /* and enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
+ /* and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
- /*--------------------------------------------------------------------------+
+ /*
* Set up Configuration registers
- *--------------------------------------------------------------------------*/
+ */
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
@@ -515,51 +500,49 @@ void pci_target_init(struct pci_controller *hose)
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
-/*************************************************************************
- * pci_master_init
- *
- ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
- /*--------------------------------------------------------------------------+
- | Write the PowerPC440 EP PCI Configuration regs.
- | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- | Enable PowerPC440 EP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------------------*/
+ /*
+ * Write the PowerPC440 EP PCI Configuration regs.
+ * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ */
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
+
+/*
+ * is_pci_host
*
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
*
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
*
- ************************************************************************/
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Cactus is always configured as host. */
return (1);
}
-#endif /* defined(CONFIG_PCI) */
+#endif /* defined(CONFIG_PCI) */
+
+
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
@@ -571,6 +554,7 @@ int post_hotkeys_pressed(void)
}
#endif /* CONFIG_POST */
+
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
--
1.5.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH] ppc4xx: Sequoia coding style cleanup and beautification
2008-01-15 22:17 ` [U-Boot-Users] [PATCH] ppc4xx: Sequoia coding style cleanup and beautification Matthias Fuchs
@ 2008-01-16 7:31 ` Stefan Roese
2008-01-16 9:33 ` [U-Boot-Users] [PATCH V2] " Matthias Fuchs
0 siblings, 1 reply; 24+ messages in thread
From: Stefan Roese @ 2008-01-16 7:31 UTC (permalink / raw)
To: u-boot
On Tuesday 15 January 2008, Matthias Fuchs wrote:
> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Thanks.
One thing I don't like (anymore) though: You patch adds 2 newlines between the
functions. I prefer 1 empty line now. Could you please resend the patch with
only 1 newline between the functions?
Thanks.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V2] ppc4xx: Sequoia coding style cleanup and beautification
2008-01-16 7:31 ` Stefan Roese
@ 2008-01-16 9:33 ` Matthias Fuchs
2008-01-16 10:33 ` Stefan Roese
0 siblings, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-16 9:33 UTC (permalink / raw)
To: u-boot
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
board/amcc/sequoia/init.S | 7 +-
board/amcc/sequoia/sequoia.c | 246 +++++++++++++++++++-----------------------
2 files changed, 114 insertions(+), 139 deletions(-)
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index ff6ae66..563f518 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -1,4 +1,6 @@
/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr at denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,7 +25,7 @@
#include <asm-ppc/mmu.h>
#include <config.h>
-/**************************************************************************
+/*
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
@@ -31,8 +33,7 @@
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
- *
- *************************************************************************/
+ */
.section .bootpg,"ax"
.globl tlbtab
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index e46efef..ce0537f 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -4,7 +4,7 @@
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol at fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel at fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel at fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -29,11 +29,12 @@
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/bitops.h>
#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
ulong flash_get_size (ulong base, int banknum);
@@ -46,9 +47,9 @@ int board_early_init_f(void)
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
- /*--------------------------------------------------------------------
+ /*
* Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
+ */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
@@ -87,9 +88,11 @@ int board_early_init_f(void)
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_4;
mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_4;
mtsdr(SDR0_PFC2, sdr0_pfc2);
mtsdr(SDR0_PFC1, sdr0_pfc1);
@@ -109,9 +112,6 @@ int board_early_init_f(void)
return 0;
}
-/*---------------------------------------------------------------------------+
- | misc_init_r.
- +---------------------------------------------------------------------------*/
int misc_init_r(void)
{
uint pbcr;
@@ -124,11 +124,7 @@ int misc_init_r(void)
char *act = getenv("usbact");
#endif
- /*
- * FLASH stuff...
- */
-
- /* Re-do sizing to get full correct info */
+ /* Re-do flash sizing to get full correct info */
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@@ -140,32 +136,7 @@ int misc_init_r(void)
mtdcr(ebccfga, pb0cr);
#endif
pbcr = mfdcr(ebccfgd);
- switch (gd->bd->bi_flashsize) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- case 32 << 20:
- size_val = 5;
- break;
- case 64 << 20:
- size_val = 6;
- break;
- case 128 << 20:
- size_val = 7;
- break;
- }
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(ebccfga, pb3cr);
@@ -197,7 +168,7 @@ int misc_init_r(void)
* USB suff...
*/
#ifdef CONFIG_440EPX
- if (act == NULL || strcmp(act, "hostdev") == 0) {
+ if (act == NULL || strcmp(act, "hostdev") == 0) {
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB2D0CR, usb2d0cr);
@@ -205,27 +176,32 @@ int misc_init_r(void)
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
- /* An 8-bit/60MHz interface is the only possible alternative
- when connecting the Device to the PHY */
+ /*
+ * An 8-bit/60MHz interface is the only possible alternative
+ * when connecting the Device to the PHY
+ */
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
- /* To enable the USB 2.0 Device function through the UTMI interface */
+ /*
+ * To enable the USB 2.0 Device function
+ * through the UTMI interface
+ */
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
@@ -245,13 +221,13 @@ int misc_init_r(void)
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
udelay (1000);
@@ -276,31 +252,31 @@ int misc_init_r(void)
mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1);
- /*clear resets*/
+ /* clear resets */
udelay (1000);
mtsdr(SDR0_SRST1, 0x00000000);
udelay (1000);
@@ -398,43 +374,42 @@ void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
}
#endif
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
+/*
+ * pci_pre_init
*
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
*
- ************************************************************************/
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB3 devices to 0.
- | Set PLB3 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
+ /*
+ * Set priority for all PLB3 devices to 0.
+ * Set PLB3 arbiter to fair mode.
+ */
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB4 devices to 0.
- +-------------------------------------------------------------------------*/
+ /*
+ * Set priority for all PLB4 devices to 0.
+ */
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
- /*-------------------------------------------------------------------------+
- | Set Nebula PLB4 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
+ /*
+ * Set Nebula PLB4 arbiter to fair mode.
+ */
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
@@ -456,47 +431,51 @@ int pci_pre_init(struct pci_controller *hose)
}
#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
+/*
+ * pci_target_init
*
- ************************************************************************/
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
- /*--------------------------------------------------------------------------+
+ /*
* Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440EPX PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ */
+ /*
+ * PowerPC440EPX PCI Master configuration.
+ * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ * PLB address 0xA0000000-0xDFFFFFFF
+ * ==> PCI address 0xA0000000-0xDFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ * Make this region non-prefetchable.
+ */
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
+ /* and enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
+ /* and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
- /*--------------------------------------------------------------------------+
+ /*
* Set up Configuration registers
- *--------------------------------------------------------------------------*/
+ */
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
@@ -515,51 +494,46 @@ void pci_target_init(struct pci_controller *hose)
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-/*************************************************************************
- * pci_master_init
- *
- ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
- /*--------------------------------------------------------------------------+
- | Write the PowerPC440 EP PCI Configuration regs.
- | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- | Enable PowerPC440 EP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------------------*/
+ /*
+ * Write the PowerPC440 EP PCI Configuration regs.
+ * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ */
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
+/*
+ * is_pci_host
*
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
*
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
*
- ************************************************************************/
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Cactus is always configured as host. */
return (1);
}
-#endif /* defined(CONFIG_PCI) */
+#endif /* defined(CONFIG_PCI) */
+
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
--
1.5.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V2] ppc4xx: Sequoia coding style cleanup and beautification
2008-01-16 9:33 ` [U-Boot-Users] [PATCH V2] " Matthias Fuchs
@ 2008-01-16 10:33 ` Stefan Roese
0 siblings, 0 replies; 24+ messages in thread
From: Stefan Roese @ 2008-01-16 10:33 UTC (permalink / raw)
To: u-boot
On Wednesday 16 January 2008, Matthias Fuchs wrote:
> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Applied, thanks.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V2] ppc4xx: Add DU440 board support
2008-01-13 22:08 ` Wolfgang Denk
2008-01-14 8:58 ` Matthias Fuchs
@ 2008-01-16 10:47 ` Matthias Fuchs
[not found] ` <200801161219.08916.sr@denx.de>
2008-01-16 10:47 ` [U-Boot-Users] [PATCH V2] ppc4xx: Complete " Matthias Fuchs
2 siblings, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-16 10:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
board/esd/du440/Makefile | 51 +++
board/esd/du440/config.mk | 41 ++
board/esd/du440/du440.c | 1018 ++++++++++++++++++++++++++++++++++++++++++++
board/esd/du440/du440.h | 42 ++
board/esd/du440/init.S | 81 ++++
board/esd/du440/u-boot.lds | 145 +++++++
6 files changed, 1378 insertions(+), 0 deletions(-)
create mode 100644 board/esd/du440/Makefile
create mode 100644 board/esd/du440/config.mk
create mode 100644 board/esd/du440/du440.c
create mode 100644 board/esd/du440/du440.h
create mode 100644 board/esd/du440/init.S
create mode 100644 board/esd/du440/u-boot.lds
diff --git a/board/esd/du440/Makefile b/board/esd/du440/Makefile
new file mode 100644
index 0000000..e996a0a
--- /dev/null
+++ b/board/esd/du440/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esd/du440/config.mk b/board/esd/du440/config.mk
new file mode 100644
index 0000000..e62b8d3
--- /dev/null
+++ b/board/esd/du440/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
new file mode 100644
index 0000000..49213ad
--- /dev/null
+++ b/board/esd/du440/du440.c
@@ -0,0 +1,1018 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <i2c.h>
+#include <ppc440.h>
+#include "du440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern ulong flash_get_size (ulong base, int banknum);
+
+int usbhub_init(void);
+int dvi_init(void);
+int eeprom_write_enable (unsigned dev_addr, int state);
+int board_revision(void);
+
+static int du440_post_errors;
+
+int board_early_init_f(void)
+{
+ u32 sdr0_cust0;
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, 0xb8400000);
+
+ /*
+ * Setup the GPIO pins
+ */
+ out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_OSRL, 0x50055400);
+ out_be32((void*)GPIO0_OSRH, 0x550050aa);
+ out_be32((void*)GPIO0_TSRL, 0x50055400);
+ out_be32((void*)GPIO0_TSRH, 0x55005000);
+ out_be32((void*)GPIO0_ISR1L, 0x50000000);
+ out_be32((void*)GPIO0_ISR1H, 0x00000000);
+ out_be32((void*)GPIO0_ISR2L, 0x00000000);
+ out_be32((void*)GPIO0_ISR2H, 0x00000100);
+ out_be32((void*)GPIO0_ISR3L, 0x00000000);
+ out_be32((void*)GPIO0_ISR3H, 0x00000000);
+
+ out_be32((void*)GPIO1_OR, 0x00000000);
+ out_be32((void*)GPIO1_TCR, 0xc2000000 |
+ CFG_GPIO1_IORSTN |
+ CFG_GPIO1_LEDUSR1 |
+ CFG_GPIO1_LEDUSR2 |
+ CFG_GPIO1_LEDPOST |
+ CFG_GPIO1_LEDDU);
+ out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
+
+ out_be32((void*)GPIO1_OSRL, 0x5c280000);
+ out_be32((void*)GPIO1_OSRH, 0x00000000);
+ out_be32((void*)GPIO1_TSRL, 0x0c000000);
+ out_be32((void*)GPIO1_TSRH, 0x00000000);
+ out_be32((void*)GPIO1_ISR1L, 0x00005550);
+ out_be32((void*)GPIO1_ISR1H, 0x00000000);
+ out_be32((void*)GPIO1_ISR2L, 0x00050000);
+ out_be32((void*)GPIO1_ISR2H, 0x00000000);
+ out_be32((void*)GPIO1_ISR3L, 0x01400000);
+ out_be32((void*)GPIO1_ISR3H, 0x00000000);
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ /*
+ * UIC1:
+ * bit30: ext. Irq 1: PLD : int 32+30
+ */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xfffffffd);
+ mtdcr(uic1tr, 0x00000000);
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ /*
+ * UIC2
+ * bit3: ext. Irq 2: DCF77 : int 64+3
+ */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+
+ /* setup EMAC bridge interface */
+ if (board_revision() == 0) {
+ /* 1 x MII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_1_2;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_1_2;
+ } else {
+ /* 2 x SMII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_6;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_6;
+ }
+
+ /* enable 2nd IIC */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* PCI arbiter enabled */
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg);
+
+ /* setup NAND FLASH */
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ (0x80000000 >> (28 + CFG_NAND0_CS)) |
+ (0x80000000 >> (28 + CFG_NAND1_CS));
+ mtsdr(SDR0_CUST0, sdr0_cust0);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val = 0;
+ u32 reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ int i, j;
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(ebccfga, pb0cr);
+ mtdcr(ebccfgd, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /*
+ * USB suff...
+ */
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+ /* An 8-bit/60MHz interface is the only possible alternative
+ when connecting the Device to the PHY */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+ /* To enable the USB 2.0 Device function through the UTMI interface */
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /* clear resets */
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy)\n");
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
+ mtdcr(plb4_acr, reg);
+
+ /*
+ * release IO-RST#
+ * We have to wait at least 560ms until we may call usbhub_init
+ */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN);
+
+ /*
+ * flash USR1/2 LEDs (600ms)
+ * This results in the necessary delay from IORST# until
+ * calling usbhub_init will succeed
+ */
+ for (j = 0; j < 3; j++) {
+ out_be32((void*)GPIO1_OR,
+ (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR2) |
+ CFG_GPIO1_LEDUSR1);
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+
+ out_be32((void*)GPIO1_OR,
+ (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR1) |
+ CFG_GPIO1_LEDUSR2);
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+ }
+
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
+ ~(CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2));
+
+ if (usbhub_init())
+ du440_post_errors++;
+
+ if(dvi_init())
+ du440_post_errors++;
+
+ return 0;
+}
+
+int pld_revision(void)
+{
+ out8(CFG_CPLD_BASE, 0x00);
+ return (int)(in8(CFG_CPLD_BASE) & CPLD_VERSION_MASK);
+}
+
+int board_revision(void)
+{
+ int rpins = (int)((in_be32((void*)GPIO1_IR) & CFG_GPIO1_HWVER_MASK)
+ >> CFG_GPIO1_HWVER_SHIFT);
+
+ return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
+ ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
+}
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void board_show_activity (ulong timestamp)
+{
+ if ((timestamp % 100) == 0)
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) ^ CFG_GPIO1_LEDUSR1);
+}
+
+void show_activity(int arg)
+{
+}
+#endif /* CONFIG_SHOW_ACTIVITY */
+
+int du440_phy_addr(int devnum)
+{
+ if (board_revision() == 0)
+ return devnum;
+
+ return devnum + 1;
+}
+
+int checkboard(void)
+{
+ char serno[32];
+
+ puts("Board: DU440");
+
+ if (getenv_r("serial#", serno, sizeof(serno)) > 0) {
+ puts(", serial# ");
+ puts(serno);
+ }
+
+ printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
+ board_revision(), pld_revision());
+ return (0);
+}
+
+/*
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long addr;
+
+ /*
+ * Set priority for all PLB3 devices to 0.
+ * Set PLB3 arbiter to fair mode.
+ */
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*
+ * Set priority for all PLB4 devices to 0.
+ */
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*
+ * Set Nebula PLB4 arbiter to fair mode.
+ */
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*
+ * Set up Direct MMIO registers
+ */
+ /*
+ * PowerPC440EPX PCI Master configuration.
+ * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ * PLB address 0xA0000000-0xDFFFFFFF
+ * ==> PCI address 0xA0000000-0xDFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ * Make this region non-prefetchable.
+ */
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
+ /* and enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
+ /* and enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*
+ * Set up Configuration registers
+ */
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ PCI_VENDOR_ID_ESDGMBH);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
+
+ pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*
+ * Write the PowerPC440 EP PCI Configuration regs.
+ * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ */
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* always configured as host. */
+ return (1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+int last_stage_init(void)
+{
+ int e, i;
+ /* everyting is ok: turn on POST-LED */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+
+ /* slowly blink on errors and finally keep LED off */
+ for (e = 0; e < du440_post_errors; e++) {
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDPOST);
+
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_I2C_MULTI_BUS)
+/*
+ * read field strength from I2C ADC
+ */
+int dcf77_status(void)
+{
+ unsigned int oldbus;
+ uchar u[2];
+ int U;
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(1);
+
+ if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
+ I2C_SET_BUS(oldbus);
+ return -1;
+ }
+
+ U = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
+
+ I2C_SET_BUS(oldbus);
+ return U;
+}
+
+int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int U;
+ u32 pin, pinold;
+ unsigned long long t1, t2;
+ bd_t *bd = gd->bd;
+
+ printf("DCF77: ");
+ U = dcf77_status();
+ if (U > 0)
+ printf("signal=%d mV\n", U);
+ else
+ printf("ERROR - no signal\n");
+
+ t1 = t2 = 0;
+ pinold = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+ while (!ctrlc()) {
+ pin = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+ if (pin && !pinold) { /* bit start */
+ t1 = get_ticks();
+ if (t2 && ((unsigned int)(t1 - t2) /
+ (bd->bi_procfreq / 1000) >= 1800))
+ printf("Start of minute\n");
+
+ t2 = t1;
+ }
+ if (t1 && !pin && pinold) { /* bit end */
+ printf("%5d\n", (unsigned int)(get_ticks() - t1) /
+ (bd->bi_procfreq / 1000));
+ }
+ pinold = pin;
+ }
+
+ printf("Abort\n");
+ return 0;
+}
+U_BOOT_CMD(
+ dcf77, 1, 1, do_dcf77,
+ "dcf77 - Check DCF77 receiver\n",
+ NULL
+ );
+
+/*
+ * initialize USB hub via I2C1
+ */
+int usbhub_init(void)
+{
+ int reg;
+ int ret = 0;
+ unsigned int oldbus;
+ uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
+ 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
+ 0x32};
+
+ uchar stcd;
+
+ printf("Hub: ");
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(1);
+
+ for (reg = 0; reg < sizeof(u); reg++)
+ if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
+ ret = -1;
+ break;
+ }
+
+ if (ret == 0) {
+ stcd = 0x03;
+ if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
+ ret = -1;
+ }
+
+ if (ret == 0)
+ printf("initialized\n");
+ else
+ printf("failed - cannot initialize USB hub\n");
+
+ I2C_SET_BUS(oldbus);
+ return ret;
+}
+
+int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ usbhub_init();
+ return 0;
+}
+U_BOOT_CMD(
+ hubinit, 1, 1, do_hubinit,
+ "hubinit - Initialize USB hub\n",
+ NULL
+ );
+#endif /* CONFIG_I2C_MULTI_BUS */
+
+#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int boot_eeprom_write (unsigned dev_addr,
+ unsigned offset,
+ uchar *buffer,
+ unsigned cnt)
+{
+ unsigned end = offset + cnt;
+ unsigned blk_off;
+ int rcode = 0;
+
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 1);
+#endif
+ /*
+ * Write data until done or would cross a write page boundary.
+ * We must write the address again when changing pages
+ * because the address counter only increments within a page.
+ */
+
+ while (offset < end) {
+ unsigned alen, len;
+ unsigned maxlen;
+
+ uchar addr[2];
+
+ blk_off = offset & 0xFF; /* block offset */
+
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
+ addr[0] |= dev_addr; /* insert device address */
+
+ len = end - offset;
+
+ /*
+ * For a FRAM device there is no limit on the number of the
+ * bytes that can be ccessed with the single read or write
+ * operation.
+ */
+#if defined(CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+
+#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+ maxlen = BOOT_EEPROM_PAGE_SIZE -
+ BOOT_EEPROM_PAGE_OFFSET(blk_off);
+#else
+ maxlen = 0x100 - blk_off;
+#endif
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
+
+ if (len > maxlen)
+ len = maxlen;
+
+ if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
+ rcode = 1;
+
+ buffer += len;
+ offset += len;
+
+#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+ }
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 0);
+#endif
+ return rcode;
+}
+
+int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong sdsdp[4];
+
+ if (argc > 1) {
+ if (!strcmp(argv[1], "533")) {
+ printf("Bootstrapping for 533MHz\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+ sdsdp[1] = 0x095fa030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "533-66")) {
+ printf("Bootstrapping for 533MHz (66MHz PCI)\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
+ sdsdp[1] = 0x0957a030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "667")) {
+ printf("Bootstrapping for 667MHz\n");
+ sdsdp[0] = 0x8778a256;
+ /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
+ sdsdp[1] = 0x0947a030;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
+ * -> not working when overclocking 533MHz chips
+ * -> untested on 667MHz chips */
+ /* sdsdp[1]=0x095fa030; */
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ }
+ } else {
+ printf("Bootstrapping for 533MHz (default)\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+ sdsdp[1] = 0x095fa030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ }
+
+ printf("Writing boot EEPROM ...\n");
+ if (boot_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
+ 0, (uchar*)sdsdp, 16) != 0)
+ printf("boot_eeprom_write failed\n");
+ else
+ printf("done (dump via 'i2c md 52 0.1 10')\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ sbe, 2, 0, do_setup_boot_eeprom,
+ "sbe - setup boot eeprom\n",
+ NULL
+ );
+
+#if defined(CFG_EEPROM_WREN)
+/*
+ * Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
+ (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr))
+ return -1;
+ else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CFG_GPIO0_EP_EEP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CFG_GPIO0_EP_EEP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void*)GPIO0_OR) &
+ CFG_GPIO0_EP_EEP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0)
+ puts ("Query of write access state failed.\n");
+ else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0)
+ puts ("Setup of write access state failed.\n");
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+static int got_pldirq;
+
+static int pld_interrupt(u32 arg)
+{
+ int rc = -1; /* not for us */
+ u8 status = in8(CFG_CPLD_BASE);
+
+ /* check for PLD interrupt */
+ if (status & PWR_INT_FLAG) {
+ /* reset this int */
+ out8(CFG_CPLD_BASE, 0);
+ rc = 0;
+ got_pldirq = 1; /* trigger backend */
+ }
+
+ return rc;
+}
+
+int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ got_pldirq = 0;
+
+ /* clear any pending interrupt */
+ out8(CFG_CPLD_BASE, 0);
+
+ irq_install_handler(CPLD_IRQ,
+ (interrupt_handler_t *)pld_interrupt, 0);
+
+ printf("Waiting ...\n");
+ while(!got_pldirq) {
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ break;
+ }
+ }
+ if (got_pldirq) {
+ printf("Got interrupt!\n");
+ printf("Power %sready!\n",
+ in8(CFG_CPLD_BASE) & PWR_RDY ? "":"NOT ");
+ }
+
+ irq_free_handler(CPLD_IRQ);
+ return 0;
+}
+U_BOOT_CMD(
+ wpi, 1, 1, do_waitpwrirq,
+ "wpi - Wait for power change interrupt\n",
+ NULL
+ );
+
+/*
+ * initialize DVI panellink transmitter
+ */
+int dvi_init(void)
+{
+ int i;
+ int ret = 0;
+ unsigned int oldbus;
+ uchar u[] = {0x08, 0x34,
+ 0x09, 0x20,
+ 0x0a, 0x90,
+ 0x0c, 0x89,
+ 0x08, 0x35};
+
+ printf("DVI: ");
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(0);
+
+ for (i = 0; i < sizeof(u); i += 2)
+ if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
+ ret = -1;
+ break;
+ }
+
+ if (ret == 0)
+ printf("initialized\n");
+ else
+ printf("failed - cannot initialize DVI transmitter\n");
+
+ I2C_SET_BUS(oldbus);
+ return ret;
+}
+
+int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ dvi_init();
+ return 0;
+}
+U_BOOT_CMD(
+ dviinit, 1, 1, do_dviinit,
+ "dviinit - Initialize DVI Panellink transmitter\n",
+ NULL
+ );
+
+/*
+ * TODO: 'time' command might be useful for others as well.
+ * Move to 'common' directory.
+ */
+int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long long start, end;
+ char c, cmd[CFG_CBSIZE];
+ char *p, *d = cmd;
+ int ret, i;
+ ulong us;
+
+ for (i = 1; i < argc; i++) {
+ p = argv[i];
+
+ if (i > 1)
+ *d++ = ' ';
+
+ while ((c = *p++) != '\0') {
+ *d++ = c;
+ }
+ }
+ *d = '\0';
+
+ start = get_ticks();
+ ret = run_command (cmd, 0);
+ end = get_ticks();
+
+ printf("ticks=%d\n", (ulong)(end - start));
+ us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
+ printf("usec=%d\n", us);
+
+ return ret;
+}
+U_BOOT_CMD(
+ time, CFG_MAXARGS, 1, do_time,
+ "time - run command and output execution time\n",
+ NULL
+ );
+
+extern void video_hw_rectfill (
+ unsigned int bpp, /* bytes per pixel */
+ unsigned int dst_x, /* dest pos x */
+ unsigned int dst_y, /* dest pos y */
+ unsigned int dim_x, /* frame width */
+ unsigned int dim_y, /* frame height */
+ unsigned int color /* fill color */
+ );
+
+/*
+ * graphics demo
+ * draw rectangles using pseudorandom number generator
+ * (see http://www.embedded.com/columns/technicalinsights/20900500)
+ */
+unsigned int rprime = 9972;
+static unsigned int r;
+static unsigned int Y;
+
+unsigned int prng(unsigned int max)
+{
+ if (r == 0 || r == 1 || r == -1)
+ r = rprime; /* keep from getting stuck */
+
+ r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
+ Y = (r >> 16) % max; /* choose upper bits and reduce */
+ return Y;
+}
+
+int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int color;
+ unsigned int x, y, dx, dy;
+
+ while (!ctrlc()) {
+ x = prng(1280 - 1);
+ y = prng(1024 - 1);
+ dx = prng(1280- x - 1);
+ dy = prng(1024 - y - 1);
+ color = prng(0x10000);
+ video_hw_rectfill(2, x, y, dx, dy, color);
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ gfxdemo, CFG_MAXARGS, 1, do_gfxdemo,
+ "gfxdemo - demo\n",
+ NULL
+ );
diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h
new file mode 100644
index 0000000..5c362e4
--- /dev/null
+++ b/board/esd/du440/du440.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDR0_USB0 0x0320 /* USB Control Register */
+
+#define CFG_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
+#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
+
+#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
+
+#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
+#define CFG_GPIO1_HWVER_SHIFT 4
+#define CFG_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
+#define CFG_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
+#define CFG_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
+#define CFG_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
+
+#define CPLD_VERSION_MASK 0x0f
+#define PWR_INT_FLAG 0x80
+#define PWR_RDY 0x10
+
+#define CPLD_IRQ (32+30)
+
+#define PCI_VENDOR_ID_ESDGMBH 0x12fe
+#define PCI_DEVICE_ID_DU440 0x0444
diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
new file mode 100644
index 0000000..4390b50
--- /dev/null
+++ b/board/esd/du440/init.S
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm-ppc/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ */
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entry for PCI IO */
+ tlbentry( CFG_PCI_IOBASE, SZ_64K, CFG_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entries for EBC: CPLD, DUMEM, DUIO */
+ tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_DUMEM_BASE, SZ_1M, CFG_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_DUIO_BASE, SZ_64K, CFG_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for NAND */
+ tlbentry( CFG_NAND0_ADDR, SZ_1K, CFG_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_NAND1_ADDR, SZ_1K, CFG_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /* TLB-entry PCI registers */
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ tlbtab_end
diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds
new file mode 100644
index 0000000..e140737
--- /dev/null
+++ b/board/esd/du440/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
--
1.5.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V2] ppc4xx: Complete DU440 board support
2008-01-13 22:08 ` Wolfgang Denk
2008-01-14 8:58 ` Matthias Fuchs
2008-01-16 10:47 ` [U-Boot-Users] [PATCH V2] " Matthias Fuchs
@ 2008-01-16 10:47 ` Matthias Fuchs
2008-01-16 11:20 ` Stefan Roese
2 siblings, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-16 10:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 3 +
include/configs/DU440.h | 438 +++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 443 insertions(+), 0 deletions(-)
create mode 100644 include/configs/DU440.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2ef2f5c..1996688 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -150,6 +150,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
DASA_SIM IOP480 (PPC401)
DP405 PPC405EP
DU405 PPC405GP
+ DU440 PPC440EPx
G2000 PPC405EP
HH405 PPC405EP
HUB405 PPC405EP
diff --git a/MAKEALL b/MAKEALL
index ebc5a22..0777dac 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -175,6 +175,7 @@ LIST_4xx=" \
DASA_SIM \
DP405 \
DU405 \
+ DU440 \
ebony \
ERIC \
EXBITGEN \
diff --git a/Makefile b/Makefile
index 1983ca0..7de2286 100644
--- a/Makefile
+++ b/Makefile
@@ -1191,6 +1191,9 @@ DP405_config: unconfig
DU405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx du405 esd
+DU440_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx du440 esd
+
ebony_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ebony amcc
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
new file mode 100644
index 0000000..30ac437
--- /dev/null
+++ b/include/configs/DU440.h
@@ -0,0 +1,438 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * based on the Sequoia board configuration by
+ * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * DU440.h - configuration for esd DU440 board (PowerPC440EPx)
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_DU440 1 /* Board is esd DU440 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */
+#define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+#define CFG_PCI_IOBASE 0xe8000000
+
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+/* TODO: external clock oscillator will be removed */
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Video Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
+#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
+#define CFG_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
+#define CFG_CONSOLE_IS_IN_ENV
+#define CFG_ISA_IO CFG_PCI_IOBASE
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#if 0
+#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
+#endif
+#define CONFIG_DDR_ECC /* Use ECC when available */
+#define SPD_EEPROM_ADDRESS {0x50}
+#define CONFIG_PROG_SDRAM_TLB
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CONFIG_I2C_CMD_TREE 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+#define CFG_SPD_BUS_NUM 0
+#define IIC1_MCP3021_ADDR 0x4d
+#define IIC1_USB2507_ADDR 0x2c
+#ifdef CONFIG_I2C_MULTI_BUS
+#define CFG_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
+#endif
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR 0x54
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+
+#define CFG_EEPROM_WREN 1
+#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
+
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the TMP401
+ */
+#define CONFIG_DTT_SENSORS { 0, 1 }
+
+/*
+ * The PMC440 uses a TI TMP401 temperature sensor. This part
+ * is basically compatible to the ADM1021 that is supported
+ * by U-Boot.
+ *
+ * - i2c addr 0x4c
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
+ */
+#define CONFIG_DTT_ADM1021
+#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1338
+#define CFG_I2C_RTC_ADDR 0x68
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethrotate=no\0" \
+ "hostname=du440\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_self=run ramargs addip addtty optargs;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
+ "bootm\0" \
+ "rootpath=/tftpboot/du440/target_root_du440\0" \
+ "img=/tftpboot/du440/uImage\0" \
+ "kernel_addr=FFC00000\0" \
+ "ramdisk_addr=FFE00000\0" \
+ "initrd_high=30000000\0" \
+ "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
+ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
+ "cp.b 100000 FFFA0000 60000\0" \
+ ""
+#if 0
+#define CONFIG_BOOTCOMMAND "run flash_self"
+#endif
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#ifndef __ASSEMBLY__
+int du440_phy_addr(int devnum);
+#endif
+
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 128 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR du440_phy_addr(1)
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CFG_OHCI_BE_CONTROLLER
+
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
+#define CFG_USB_OHCI_SLOT_NAME "du440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_SUPPORT_VFAT
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+
+#define CFG_CPLD_BASE 0xC0000000
+#define CFG_CPLD_RANGE 0x00000010
+#define CFG_DUMEM_BASE 0xC0100000
+#define CFG_DUMEM_RANGE 0x00100000
+#define CFG_DUIO_BASE 0xC0200000
+#define CFG_DUIO_RANGE 0x00010000
+
+/*
+ * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
+ */
+#define CFG_NAND0_CS 2 /* NAND chip connected to CSx */
+#define CFG_NAND1_CS 3 /* NAND chip connected to CSx */
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x04017200 /* mf test-only - disabled ready# */
+/* 0x03017200 = 90ns */ /* mf test-only - use 0x04017200 for 120ns */
+#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
+
+/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
+#define CFG_EBC_PB1AP 0x018003c0
+#define CFG_EBC_PB1CR (CFG_CPLD_BASE | 0x18000)
+
+/* Memory Bank 2 (NAND-FLASH) initialization */
+#define CFG_EBC_PB2AP 0x018003c0
+#define CFG_EBC_PB2CR (CFG_NAND0_ADDR | 0x1c000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x018003c0
+#define CFG_EBC_PB3CR (CFG_NAND1_ADDR | 0x1c000)
+
+/* Memory Bank 4 (DUMEM, 1MB) initialization */
+#define CFG_EBC_PB4AP 0x018053c0
+#define CFG_EBC_PB4CR (CFG_DUMEM_BASE | 0x18000)
+
+/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
+#define CFG_EBC_PB5AP 0x018053c0
+#define CFG_EBC_PB5CR (CFG_DUIO_BASE | 0x18000)
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE 2
+#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CFG_NAND_BASE_LIST {CFG_NAND0_ADDR + CFG_NAND0_CS, CFG_NAND1_ADDR + CFG_NAND1_CS}
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#if 0
+#define CONFIG_SHOW_ACTIVITY 1
+#endif
+
+#endif /* __CONFIG_H */
--
1.5.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V2] ppc4xx: Complete DU440 board support
2008-01-16 10:47 ` [U-Boot-Users] [PATCH V2] ppc4xx: Complete " Matthias Fuchs
@ 2008-01-16 11:20 ` Stefan Roese
2008-01-16 12:00 ` [U-Boot-Users] [PATCH V3] " Matthias Fuchs
0 siblings, 1 reply; 24+ messages in thread
From: Stefan Roese @ 2008-01-16 11:20 UTC (permalink / raw)
To: u-boot
On Wednesday 16 January 2008, Matthias Fuchs wrote:
> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Comments below.
> MAINTAINERS | 1 +
> MAKEALL | 1 +
> Makefile | 3 +
> include/configs/DU440.h | 438
> +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 443
> insertions(+), 0 deletions(-)
> create mode 100644 include/configs/DU440.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2ef2f5c..1996688 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -150,6 +150,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
> DASA_SIM IOP480 (PPC401)
> DP405 PPC405EP
> DU405 PPC405GP
> + DU440 PPC440EPx
> G2000 PPC405EP
> HH405 PPC405EP
> HUB405 PPC405EP
> diff --git a/MAKEALL b/MAKEALL
> index ebc5a22..0777dac 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -175,6 +175,7 @@ LIST_4xx=" \
> DASA_SIM \
> DP405 \
> DU405 \
> + DU440 \
> ebony \
> ERIC \
> EXBITGEN \
> diff --git a/Makefile b/Makefile
> index 1983ca0..7de2286 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1191,6 +1191,9 @@ DP405_config: unconfig
> DU405_config: unconfig
> @$(MKCONFIG) $(@:_config=) ppc ppc4xx du405 esd
>
> +DU440_config: unconfig
> + @$(MKCONFIG) $(@:_config=) ppc ppc4xx du440 esd
> +
> ebony_config: unconfig
> @$(MKCONFIG) $(@:_config=) ppc ppc4xx ebony amcc
>
> diff --git a/include/configs/DU440.h b/include/configs/DU440.h
> new file mode 100644
> index 0000000..30ac437
> --- /dev/null
> +++ b/include/configs/DU440.h
> @@ -0,0 +1,438 @@
> +/*
> + * (C) Copyright 2008
> + * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
> + *
> + * based on the Sequoia board configuration by
> + * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/************************************************************************
> + * DU440.h - configuration for esd DU440 board (PowerPC440EPx)
> + ***********************************************************************/
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*-----------------------------------------------------------------------
> + * High Level Configuration Options
> + *----------------------------------------------------------------------*/
> +#define CONFIG_DU440 1 /* Board is esd DU440 */
> +#define CONFIG_440EPX 1 /* Specific PPC440EPx */
> +#define CONFIG_4xx 1 /* ... PPC4xx family */
> +#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
> +
> +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
> +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
> +#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
> +
> +/*-----------------------------------------------------------------------
> + * Base addresses -- Note these are effective addresses where the
> + * actual resources get mapped (not physical addresses)
> + *----------------------------------------------------------------------*/
> +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
> +#define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
> +
> +#define CFG_BOOT_BASE_ADDR 0xf0000000
> +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
> +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
> +#define CFG_MONITOR_BASE TEXT_BASE
> +#define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */
> +#define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */
> +#define CFG_OCM_BASE 0xe0010000 /* ocm */
> +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
> +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
> +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
> +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
> +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
> +#define CFG_PCI_IOBASE 0xe8000000
> +
> +
> +/* Don't change either of these */
> +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
> +
> +#define CFG_USB2D0_BASE 0xe0000100
> +#define CFG_USB_DEVICE 0xe0000000
> +#define CFG_USB_HOST 0xe0000400
> +
> +/*-----------------------------------------------------------------------
> + * Initial RAM & stack pointer
> + *----------------------------------------------------------------------*/
> +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
> +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
> +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
> +
> +#define CFG_INIT_RAM_END (4 << 10)
> +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
> +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
> +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
> +
> +/*-----------------------------------------------------------------------
> + * Serial Port
> + *----------------------------------------------------------------------*/
> +/* TODO: external clock oscillator will be removed */
> +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SERIAL_MULTI 1
> +#undef CONFIG_UART1_CONSOLE
> +
> +#define CFG_BAUDRATE_TABLE \
> + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
> +
> +/*-----------------------------------------------------------------------
> + * Video Port
> + *----------------------------------------------------------------------*/
> +#define CONFIG_VIDEO
> +#define CONFIG_VIDEO_SMI_LYNXEM
> +#define CONFIG_CFB_CONSOLE
> +#define CONFIG_VIDEO_LOGO
> +#define CONFIG_VGA_AS_SINGLE_DEVICE
> +#define CONFIG_SPLASH_SCREEN
> +#define CONFIG_SPLASH_SCREEN_ALIGN
> +#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images
> */ +#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img
> */ +#define CFG_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
> +#define CFG_CONSOLE_IS_IN_ENV
> +#define CFG_ISA_IO CFG_PCI_IOBASE
> +
> +/*-----------------------------------------------------------------------
> + * Environment
> + *----------------------------------------------------------------------*/
> +#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
> +
> +/*-----------------------------------------------------------------------
> + * FLASH related
> + *----------------------------------------------------------------------*/
> +#define CFG_FLASH_CFI /* The flash is CFI compatible */
> +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
> +
> +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
> +
> +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
> +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
> +
> +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
> +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
> +
> +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x
> faster) */ +/* CFI_FLASH_PROTECTION make flash_protect hang sometimes ->
> disabled */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash
> protection */ +
> +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
> +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
> +
> +#ifdef CFG_ENV_IS_IN_FLASH
> +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
> +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
> +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
> +
> +/* Address and size of Redundant Environment Sector */
> +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
> +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
> +#endif
> +
> +#ifdef CFG_ENV_IS_IN_EEPROM
> +#define CFG_ENV_OFFSET 0 /* environment starts at the beginning of the
> EEPROM */ +#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env
> vars*/ +#endif
> +
> +/*-----------------------------------------------------------------------
> + * DDR SDRAM
> + *----------------------------------------------------------------------*/
> +#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
> +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
> +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
> +#if 0
> +#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
> +#endif
> +#define CONFIG_DDR_ECC /* Use ECC when available */
> +#define SPD_EEPROM_ADDRESS {0x50}
> +#define CONFIG_PROG_SDRAM_TLB
> +
> +/*-----------------------------------------------------------------------
> + * I2C
> + *----------------------------------------------------------------------*/
> +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
> +#undef CONFIG_SOFT_I2C /* I2C bit-banged */
> +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
> +#define CFG_I2C_SLAVE 0x7F
> +#define CONFIG_I2C_CMD_TREE 1
> +#define CONFIG_I2C_MULTI_BUS 1
> +
> +#define CFG_SPD_BUS_NUM 0
> +#define IIC1_MCP3021_ADDR 0x4d
> +#define IIC1_USB2507_ADDR 0x2c
> +#ifdef CONFIG_I2C_MULTI_BUS
> +#define CFG_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
> +#endif
> +#define CFG_I2C_MULTI_EEPROMS
> +#define CFG_I2C_EEPROM_ADDR 0x54
> +#define CFG_I2C_EEPROM_ADDR_LEN 2
> +#define CFG_EEPROM_PAGE_WRITE_ENABLE
> +#define CFG_EEPROM_PAGE_WRITE_BITS 5
> +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
> +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
> +
> +#define CFG_EEPROM_WREN 1
> +#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
> +
> +/*
> + * standard dtt sensor configuration - bottom bit will determine local or
> + * remote sensor of the TMP401
> + */
> +#define CONFIG_DTT_SENSORS { 0, 1 }
> +
> +/*
> + * The PMC440 uses a TI TMP401 temperature sensor. This part
> + * is basically compatible to the ADM1021 that is supported
> + * by U-Boot.
> + *
> + * - i2c addr 0x4c
> + * - conversion rate 0x02 = 0.25 conversions/second
> + * - ALERT ouput disabled
> + * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
> + * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
> + */
> +#define CONFIG_DTT_ADM1021
> +#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
> +
> +/*-----------------------------------------------------------------------
> + * RTC stuff
> + *-----------------------------------------------------------------------
> + */
> +#define CONFIG_RTC_DS1338
> +#define CFG_I2C_RTC_ADDR 0x68
> +
> +#undef CONFIG_BOOTARGS
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "netdev=eth0\0" \
> + "ethrotate=no\0" \
> + "hostname=du440\0" \
> + "nfsargs=setenv bootargs root=/dev/nfs rw " \
> + "nfsroot=${serverip}:${rootpath}\0" \
> + "ramargs=setenv bootargs root=/dev/ram rw\0" \
> + "addip=setenv bootargs ${bootargs} " \
> + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> + ":${hostname}:${netdev}:off panic=1\0" \
> + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
> + "flash_self=run ramargs addip addtty optargs;" \
> + "bootm ${kernel_addr} ${ramdisk_addr}\0" \
> + "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
> + "bootm\0" \
> + "rootpath=/tftpboot/du440/target_root_du440\0" \
> + "img=/tftpboot/du440/uImage\0" \
> + "kernel_addr=FFC00000\0" \
> + "ramdisk_addr=FFE00000\0" \
> + "initrd_high=30000000\0" \
> + "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
> + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
> + "cp.b 100000 FFFA0000 60000\0" \
> + ""
> +#if 0
> +#define CONFIG_BOOTCOMMAND "run flash_self"
> +#endif
> +
> +#define CONFIG_PREBOOT /* enable preboot variable */
> +
> +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
> +
> +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> +
> +#ifndef __ASSEMBLY__
> +int du440_phy_addr(int devnum);
> +#endif
> +
> +#define CONFIG_IBM_EMAC4_V4 1
> +#define CONFIG_MII 1 /* MII PHY management */
> +#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address, See
> schematics */ +
> +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
> +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
> +
> +#define CONFIG_HAS_ETH0
> +#define CFG_RX_ETH_BUFFER 128 /* Number of ethernet rx buffers &
> descriptors */ +
> +#define CONFIG_NET_MULTI 1
> +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
> +#define CONFIG_PHY1_ADDR du440_phy_addr(1)
> +
> +/* USB */
> +#define CONFIG_USB_OHCI_NEW
> +#define CONFIG_USB_STORAGE
> +#define CFG_OHCI_BE_CONTROLLER
> +
> +#define CFG_USB_OHCI_CPU_INIT 1
> +#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
> +#define CFG_USB_OHCI_SLOT_NAME "du440"
> +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
> +
> +/* Comment this out to enable USB 1.1 device */
> +#define USB_2_0_DEVICE
> +
> +/* Partitions */
> +#define CONFIG_MAC_PARTITION
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_ISO_PARTITION
> +
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_BSP
> +#define CONFIG_CMD_DATE
> +#define CONFIG_CMD_ASKENV
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_DTT
> +#define CONFIG_CMD_DIAG
> +#define CONFIG_CMD_EEPROM
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_IRQ
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NAND
> +#define CONFIG_CMD_NET
> +#define CONFIG_CMD_NFS
> +#define CONFIG_CMD_PCI
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_USB
> +#define CONFIG_CMD_REGINFO
> +#define CONFIG_CMD_SDRAM
> +
> +#define CONFIG_SUPPORT_VFAT
> +
> +/*-----------------------------------------------------------------------
> + * Miscellaneous configurable options
> + *----------------------------------------------------------------------*/
> +#define CFG_LONGHELP /* undef to save memory */
> +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
> +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
> +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
> +#else
> +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
> +#endif
> +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /*
> Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of
> command args */
> +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
> +
> +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
> +#define CFG_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
> +
> +#define CFG_LOAD_ADDR 0x100000 /* default load address */
> +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
> +
> +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
> +
> +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
> +#define CONFIG_LOOPW 1 /* enable loopw command */
> +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
> +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0
> */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +
> +#define CONFIG_AUTOBOOT_KEYED 1
> +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d
> seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d"
> +#define CONFIG_AUTOBOOT_STOP_STR " "
> +
> +/*-----------------------------------------------------------------------
> + * PCI stuff
> + *----------------------------------------------------------------------*/
> +/* General PCI */
> +#define CONFIG_PCI /* include pci support */
> +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
> +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to
> CFG_PCI_MEMBASE*/ +
> +/* Board-specific PCI */
> +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
> +#define CFG_PCI_TARGET_INIT
> +#define CFG_PCI_MASTER_INIT
> +
> +/*
> + * For booting Linux, the board info and command line data
> + * have to be in the first 8 MB of memory, since this is
> + * the maximum mapped by the Linux kernel during initialization.
> + */
> +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
> +
> +/*-----------------------------------------------------------------------
> + * External Bus Controller (EBC) Setup
> + *----------------------------------------------------------------------*/
> +#define CFG_FLASH CFG_FLASH_BASE
> +
> +#define CFG_CPLD_BASE 0xC0000000
> +#define CFG_CPLD_RANGE 0x00000010
> +#define CFG_DUMEM_BASE 0xC0100000
> +#define CFG_DUMEM_RANGE 0x00100000
> +#define CFG_DUIO_BASE 0xC0200000
> +#define CFG_DUIO_RANGE 0x00010000
> +
> +/*
> + * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
> + */
Comment above is not correct. Please fix or remove.
> +#define CFG_NAND0_CS 2 /* NAND chip connected to CSx */
> +#define CFG_NAND1_CS 3 /* NAND chip connected to CSx */
> +/* Memory Bank 0 (NOR-FLASH) initialization */
> +#define CFG_EBC_PB0AP 0x04017200 /* mf test-only - disabled ready# */
> +/* 0x03017200 = 90ns */ /* mf test-only - use 0x04017200 for
> 120ns */ +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
> +
> +/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
> +#define CFG_EBC_PB1AP 0x018003c0
> +#define CFG_EBC_PB1CR (CFG_CPLD_BASE | 0x18000)
> +
> +/* Memory Bank 2 (NAND-FLASH) initialization */
> +#define CFG_EBC_PB2AP 0x018003c0
> +#define CFG_EBC_PB2CR (CFG_NAND0_ADDR | 0x1c000)
> +
> +/* Memory Bank 3 (NAND-FLASH) initialization */
> +#define CFG_EBC_PB3AP 0x018003c0
> +#define CFG_EBC_PB3CR (CFG_NAND1_ADDR | 0x1c000)
> +
> +/* Memory Bank 4 (DUMEM, 1MB) initialization */
> +#define CFG_EBC_PB4AP 0x018053c0
> +#define CFG_EBC_PB4CR (CFG_DUMEM_BASE | 0x18000)
> +
> +/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum)
> */ +#define CFG_EBC_PB5AP 0x018053c0
> +#define CFG_EBC_PB5CR (CFG_DUIO_BASE | 0x18000)
> +
> +/*-----------------------------------------------------------------------
> + * NAND FLASH
> + *----------------------------------------------------------------------*/
> +#define CFG_MAX_NAND_DEVICE 2
> +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
> +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
> +#define CFG_NAND_BASE_LIST {CFG_NAND0_ADDR + CFG_NAND0_CS, CFG_NAND1_ADDR
> + CFG_NAND1_CS} +
> +/*
> + * Internal Definitions
> + *
> + * Boot Flags
> + */
> +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
> +#define BOOTFLAG_WARM 0x02 /* Software reboot */
> +
> +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
> +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
> +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
> +#endif
> +
> +#if 0
> +#define CONFIG_SHOW_ACTIVITY 1
> +#endif
> +
> +#endif /* __CONFIG_H */
--
Viele Gr??e,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V2] ppc4xx: Add DU440 board support
[not found] ` <200801161219.08916.sr@denx.de>
@ 2008-01-16 11:52 ` Matthias Fuchs
2008-01-16 15:23 ` Matthias Fuchs
2008-01-16 11:59 ` [U-Boot-Users] [PATCH V3] " Matthias Fuchs
1 sibling, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-16 11:52 UTC (permalink / raw)
To: u-boot
My dear old Mr. 'mir-doch-egal',
I don't dare to remember your old times at your previous company ...
I think it would be funny for other's to post some of Stefan's code here
from his pre-Denx era. The comments would explose the list's size limit :-)
Yes, I will fix the issue below. Just a minute.
BTW, what about removing some lines when quoting such a huge patch.
On Wednesday 16 January 2008 12:19, Stefan Roese wrote:
> On Wednesday 16 January 2008, Matthias Fuchs wrote:
> > Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
>
> Still some comments below.
>
> > + if(dvi_init())
>
> Space after "(" please.
>
> > + du440_post_errors++;
> > +int last_stage_init(void)
> > +{
> > + int e, i;
>
> Empty newline after variable declaration.
>
> > + /* everyting is ok: turn on POST-LED */
> > + int U;
>
> Upper case variables? Please use something else here.
>
> > + oldbus = I2C_GET_BUS();
> > +{
> > + int U;
>
> Again.
>
> > + */
>
> Yes, please don't forget about this. Sounds interesting. :)
>
> > +int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
You are welcome to do this before me.
Matthias
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V3] ppc4xx: Add DU440 board support
[not found] ` <200801161219.08916.sr@denx.de>
2008-01-16 11:52 ` Matthias Fuchs
@ 2008-01-16 11:59 ` Matthias Fuchs
2008-01-17 7:25 ` Stefan Roese
1 sibling, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-16 11:59 UTC (permalink / raw)
To: u-boot
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
board/esd/du440/Makefile | 51 +++
board/esd/du440/config.mk | 37 ++
board/esd/du440/du440.c | 1018 ++++++++++++++++++++++++++++++++++++++++++++
board/esd/du440/du440.h | 42 ++
board/esd/du440/init.S | 81 ++++
board/esd/du440/u-boot.lds | 145 +++++++
6 files changed, 1374 insertions(+), 0 deletions(-)
create mode 100644 board/esd/du440/Makefile
create mode 100644 board/esd/du440/config.mk
create mode 100644 board/esd/du440/du440.c
create mode 100644 board/esd/du440/du440.h
create mode 100644 board/esd/du440/init.S
create mode 100644 board/esd/du440/u-boot.lds
diff --git a/board/esd/du440/Makefile b/board/esd/du440/Makefile
new file mode 100644
index 0000000..e996a0a
--- /dev/null
+++ b/board/esd/du440/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esd/du440/config.mk b/board/esd/du440/config.mk
new file mode 100644
index 0000000..5164334
--- /dev/null
+++ b/board/esd/du440/config.mk
@@ -0,0 +1,37 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
new file mode 100644
index 0000000..3b95a9c
--- /dev/null
+++ b/board/esd/du440/du440.c
@@ -0,0 +1,1018 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <i2c.h>
+#include <ppc440.h>
+#include "du440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern ulong flash_get_size (ulong base, int banknum);
+
+int usbhub_init(void);
+int dvi_init(void);
+int eeprom_write_enable (unsigned dev_addr, int state);
+int board_revision(void);
+
+static int du440_post_errors;
+
+int board_early_init_f(void)
+{
+ u32 sdr0_cust0;
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, 0xb8400000);
+
+ /*
+ * Setup the GPIO pins
+ */
+ out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_OSRL, 0x50055400);
+ out_be32((void*)GPIO0_OSRH, 0x550050aa);
+ out_be32((void*)GPIO0_TSRL, 0x50055400);
+ out_be32((void*)GPIO0_TSRH, 0x55005000);
+ out_be32((void*)GPIO0_ISR1L, 0x50000000);
+ out_be32((void*)GPIO0_ISR1H, 0x00000000);
+ out_be32((void*)GPIO0_ISR2L, 0x00000000);
+ out_be32((void*)GPIO0_ISR2H, 0x00000100);
+ out_be32((void*)GPIO0_ISR3L, 0x00000000);
+ out_be32((void*)GPIO0_ISR3H, 0x00000000);
+
+ out_be32((void*)GPIO1_OR, 0x00000000);
+ out_be32((void*)GPIO1_TCR, 0xc2000000 |
+ CFG_GPIO1_IORSTN |
+ CFG_GPIO1_LEDUSR1 |
+ CFG_GPIO1_LEDUSR2 |
+ CFG_GPIO1_LEDPOST |
+ CFG_GPIO1_LEDDU);
+ out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
+
+ out_be32((void*)GPIO1_OSRL, 0x5c280000);
+ out_be32((void*)GPIO1_OSRH, 0x00000000);
+ out_be32((void*)GPIO1_TSRL, 0x0c000000);
+ out_be32((void*)GPIO1_TSRH, 0x00000000);
+ out_be32((void*)GPIO1_ISR1L, 0x00005550);
+ out_be32((void*)GPIO1_ISR1H, 0x00000000);
+ out_be32((void*)GPIO1_ISR2L, 0x00050000);
+ out_be32((void*)GPIO1_ISR2H, 0x00000000);
+ out_be32((void*)GPIO1_ISR3L, 0x01400000);
+ out_be32((void*)GPIO1_ISR3H, 0x00000000);
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ /*
+ * UIC1:
+ * bit30: ext. Irq 1: PLD : int 32+30
+ */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xfffffffd);
+ mtdcr(uic1tr, 0x00000000);
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ /*
+ * UIC2
+ * bit3: ext. Irq 2: DCF77 : int 64+3
+ */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+
+ /* setup EMAC bridge interface */
+ if (board_revision() == 0) {
+ /* 1 x MII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_1_2;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_1_2;
+ } else {
+ /* 2 x SMII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_6;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_6;
+ }
+
+ /* enable 2nd IIC */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* PCI arbiter enabled */
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg);
+
+ /* setup NAND FLASH */
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ (0x80000000 >> (28 + CFG_NAND0_CS)) |
+ (0x80000000 >> (28 + CFG_NAND1_CS));
+ mtsdr(SDR0_CUST0, sdr0_cust0);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val = 0;
+ u32 reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ int i, j;
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(ebccfga, pb0cr);
+ mtdcr(ebccfgd, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /*
+ * USB suff...
+ */
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+ /* An 8-bit/60MHz interface is the only possible alternative
+ when connecting the Device to the PHY */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+ /* To enable the USB 2.0 Device function through the UTMI interface */
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /* clear resets */
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy)\n");
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
+ mtdcr(plb4_acr, reg);
+
+ /*
+ * release IO-RST#
+ * We have to wait at least 560ms until we may call usbhub_init
+ */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN);
+
+ /*
+ * flash USR1/2 LEDs (600ms)
+ * This results in the necessary delay from IORST# until
+ * calling usbhub_init will succeed
+ */
+ for (j = 0; j < 3; j++) {
+ out_be32((void*)GPIO1_OR,
+ (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR2) |
+ CFG_GPIO1_LEDUSR1);
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+
+ out_be32((void*)GPIO1_OR,
+ (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR1) |
+ CFG_GPIO1_LEDUSR2);
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+ }
+
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
+ ~(CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2));
+
+ if (usbhub_init())
+ du440_post_errors++;
+
+ if (dvi_init())
+ du440_post_errors++;
+
+ return 0;
+}
+
+int pld_revision(void)
+{
+ out8(CFG_CPLD_BASE, 0x00);
+ return (int)(in8(CFG_CPLD_BASE) & CPLD_VERSION_MASK);
+}
+
+int board_revision(void)
+{
+ int rpins = (int)((in_be32((void*)GPIO1_IR) & CFG_GPIO1_HWVER_MASK)
+ >> CFG_GPIO1_HWVER_SHIFT);
+
+ return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
+ ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
+}
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void board_show_activity (ulong timestamp)
+{
+ if ((timestamp % 100) == 0)
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) ^ CFG_GPIO1_LEDUSR1);
+}
+
+void show_activity(int arg)
+{
+}
+#endif /* CONFIG_SHOW_ACTIVITY */
+
+int du440_phy_addr(int devnum)
+{
+ if (board_revision() == 0)
+ return devnum;
+
+ return devnum + 1;
+}
+
+int checkboard(void)
+{
+ char serno[32];
+
+ puts("Board: DU440");
+
+ if (getenv_r("serial#", serno, sizeof(serno)) > 0) {
+ puts(", serial# ");
+ puts(serno);
+ }
+
+ printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
+ board_revision(), pld_revision());
+ return (0);
+}
+
+/*
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long addr;
+
+ /*
+ * Set priority for all PLB3 devices to 0.
+ * Set PLB3 arbiter to fair mode.
+ */
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*
+ * Set priority for all PLB4 devices to 0.
+ */
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*
+ * Set Nebula PLB4 arbiter to fair mode.
+ */
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*
+ * Set up Direct MMIO registers
+ */
+ /*
+ * PowerPC440EPX PCI Master configuration.
+ * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ * PLB address 0xA0000000-0xDFFFFFFF
+ * ==> PCI address 0xA0000000-0xDFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ * Make this region non-prefetchable.
+ */
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
+ /* and enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
+ /* and enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*
+ * Set up Configuration registers
+ */
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ PCI_VENDOR_ID_ESDGMBH);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
+
+ pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*
+ * Write the PowerPC440 EP PCI Configuration regs.
+ * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ */
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* always configured as host. */
+ return (1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+int last_stage_init(void)
+{
+ int e, i;
+
+ /* everyting is ok: turn on POST-LED */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+
+ /* slowly blink on errors and finally keep LED off */
+ for (e = 0; e < du440_post_errors; e++) {
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDPOST);
+
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_I2C_MULTI_BUS)
+/*
+ * read field strength from I2C ADC
+ */
+int dcf77_status(void)
+{
+ unsigned int oldbus;
+ uchar u[2];
+ int mv;
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(1);
+
+ if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
+ I2C_SET_BUS(oldbus);
+ return -1;
+ }
+
+ mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
+
+ I2C_SET_BUS(oldbus);
+ return mv;
+}
+
+int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int mv;
+ u32 pin, pinold;
+ unsigned long long t1, t2;
+ bd_t *bd = gd->bd;
+
+ printf("DCF77: ");
+ mv = dcf77_status();
+ if (mv > 0)
+ printf("signal=%d mV\n", mv);
+ else
+ printf("ERROR - no signal\n");
+
+ t1 = t2 = 0;
+ pinold = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+ while (!ctrlc()) {
+ pin = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+ if (pin && !pinold) { /* bit start */
+ t1 = get_ticks();
+ if (t2 && ((unsigned int)(t1 - t2) /
+ (bd->bi_procfreq / 1000) >= 1800))
+ printf("Start of minute\n");
+
+ t2 = t1;
+ }
+ if (t1 && !pin && pinold) { /* bit end */
+ printf("%5d\n", (unsigned int)(get_ticks() - t1) /
+ (bd->bi_procfreq / 1000));
+ }
+ pinold = pin;
+ }
+
+ printf("Abort\n");
+ return 0;
+}
+U_BOOT_CMD(
+ dcf77, 1, 1, do_dcf77,
+ "dcf77 - Check DCF77 receiver\n",
+ NULL
+ );
+
+/*
+ * initialize USB hub via I2C1
+ */
+int usbhub_init(void)
+{
+ int reg;
+ int ret = 0;
+ unsigned int oldbus;
+ uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
+ 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
+ 0x32};
+ uchar stcd;
+
+ printf("Hub: ");
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(1);
+
+ for (reg = 0; reg < sizeof(u); reg++)
+ if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
+ ret = -1;
+ break;
+ }
+
+ if (ret == 0) {
+ stcd = 0x03;
+ if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
+ ret = -1;
+ }
+
+ if (ret == 0)
+ printf("initialized\n");
+ else
+ printf("failed - cannot initialize USB hub\n");
+
+ I2C_SET_BUS(oldbus);
+ return ret;
+}
+
+int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ usbhub_init();
+ return 0;
+}
+U_BOOT_CMD(
+ hubinit, 1, 1, do_hubinit,
+ "hubinit - Initialize USB hub\n",
+ NULL
+ );
+#endif /* CONFIG_I2C_MULTI_BUS */
+
+#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int boot_eeprom_write (unsigned dev_addr,
+ unsigned offset,
+ uchar *buffer,
+ unsigned cnt)
+{
+ unsigned end = offset + cnt;
+ unsigned blk_off;
+ int rcode = 0;
+
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 1);
+#endif
+ /*
+ * Write data until done or would cross a write page boundary.
+ * We must write the address again when changing pages
+ * because the address counter only increments within a page.
+ */
+
+ while (offset < end) {
+ unsigned alen, len;
+ unsigned maxlen;
+
+ uchar addr[2];
+
+ blk_off = offset & 0xFF; /* block offset */
+
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
+ addr[0] |= dev_addr; /* insert device address */
+
+ len = end - offset;
+
+ /*
+ * For a FRAM device there is no limit on the number of the
+ * bytes that can be ccessed with the single read or write
+ * operation.
+ */
+#if defined(CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+
+#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+ maxlen = BOOT_EEPROM_PAGE_SIZE -
+ BOOT_EEPROM_PAGE_OFFSET(blk_off);
+#else
+ maxlen = 0x100 - blk_off;
+#endif
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
+
+ if (len > maxlen)
+ len = maxlen;
+
+ if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
+ rcode = 1;
+
+ buffer += len;
+ offset += len;
+
+#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+ }
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 0);
+#endif
+ return rcode;
+}
+
+int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong sdsdp[4];
+
+ if (argc > 1) {
+ if (!strcmp(argv[1], "533")) {
+ printf("Bootstrapping for 533MHz\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+ sdsdp[1] = 0x095fa030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "533-66")) {
+ printf("Bootstrapping for 533MHz (66MHz PCI)\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
+ sdsdp[1] = 0x0957a030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "667")) {
+ printf("Bootstrapping for 667MHz\n");
+ sdsdp[0] = 0x8778a256;
+ /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
+ sdsdp[1] = 0x0947a030;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
+ * -> not working when overclocking 533MHz chips
+ * -> untested on 667MHz chips */
+ /* sdsdp[1]=0x095fa030; */
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ }
+ } else {
+ printf("Bootstrapping for 533MHz (default)\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+ sdsdp[1] = 0x095fa030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ }
+
+ printf("Writing boot EEPROM ...\n");
+ if (boot_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
+ 0, (uchar*)sdsdp, 16) != 0)
+ printf("boot_eeprom_write failed\n");
+ else
+ printf("done (dump via 'i2c md 52 0.1 10')\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ sbe, 2, 0, do_setup_boot_eeprom,
+ "sbe - setup boot eeprom\n",
+ NULL
+ );
+
+#if defined(CFG_EEPROM_WREN)
+/*
+ * Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
+ (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr))
+ return -1;
+ else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CFG_GPIO0_EP_EEP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CFG_GPIO0_EP_EEP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void*)GPIO0_OR) &
+ CFG_GPIO0_EP_EEP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0)
+ puts ("Query of write access state failed.\n");
+ else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0)
+ puts ("Setup of write access state failed.\n");
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+static int got_pldirq;
+
+static int pld_interrupt(u32 arg)
+{
+ int rc = -1; /* not for us */
+ u8 status = in8(CFG_CPLD_BASE);
+
+ /* check for PLD interrupt */
+ if (status & PWR_INT_FLAG) {
+ /* reset this int */
+ out8(CFG_CPLD_BASE, 0);
+ rc = 0;
+ got_pldirq = 1; /* trigger backend */
+ }
+
+ return rc;
+}
+
+int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ got_pldirq = 0;
+
+ /* clear any pending interrupt */
+ out8(CFG_CPLD_BASE, 0);
+
+ irq_install_handler(CPLD_IRQ,
+ (interrupt_handler_t *)pld_interrupt, 0);
+
+ printf("Waiting ...\n");
+ while(!got_pldirq) {
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ break;
+ }
+ }
+ if (got_pldirq) {
+ printf("Got interrupt!\n");
+ printf("Power %sready!\n",
+ in8(CFG_CPLD_BASE) & PWR_RDY ? "":"NOT ");
+ }
+
+ irq_free_handler(CPLD_IRQ);
+ return 0;
+}
+U_BOOT_CMD(
+ wpi, 1, 1, do_waitpwrirq,
+ "wpi - Wait for power change interrupt\n",
+ NULL
+ );
+
+/*
+ * initialize DVI panellink transmitter
+ */
+int dvi_init(void)
+{
+ int i;
+ int ret = 0;
+ unsigned int oldbus;
+ uchar u[] = {0x08, 0x34,
+ 0x09, 0x20,
+ 0x0a, 0x90,
+ 0x0c, 0x89,
+ 0x08, 0x35};
+
+ printf("DVI: ");
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(0);
+
+ for (i = 0; i < sizeof(u); i += 2)
+ if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
+ ret = -1;
+ break;
+ }
+
+ if (ret == 0)
+ printf("initialized\n");
+ else
+ printf("failed - cannot initialize DVI transmitter\n");
+
+ I2C_SET_BUS(oldbus);
+ return ret;
+}
+
+int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ dvi_init();
+ return 0;
+}
+U_BOOT_CMD(
+ dviinit, 1, 1, do_dviinit,
+ "dviinit - Initialize DVI Panellink transmitter\n",
+ NULL
+ );
+
+/*
+ * TODO: 'time' command might be useful for others as well.
+ * Move to 'common' directory.
+ */
+int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long long start, end;
+ char c, cmd[CFG_CBSIZE];
+ char *p, *d = cmd;
+ int ret, i;
+ ulong us;
+
+ for (i = 1; i < argc; i++) {
+ p = argv[i];
+
+ if (i > 1)
+ *d++ = ' ';
+
+ while ((c = *p++) != '\0') {
+ *d++ = c;
+ }
+ }
+ *d = '\0';
+
+ start = get_ticks();
+ ret = run_command (cmd, 0);
+ end = get_ticks();
+
+ printf("ticks=%d\n", (ulong)(end - start));
+ us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
+ printf("usec=%d\n", us);
+
+ return ret;
+}
+U_BOOT_CMD(
+ time, CFG_MAXARGS, 1, do_time,
+ "time - run command and output execution time\n",
+ NULL
+ );
+
+extern void video_hw_rectfill (
+ unsigned int bpp, /* bytes per pixel */
+ unsigned int dst_x, /* dest pos x */
+ unsigned int dst_y, /* dest pos y */
+ unsigned int dim_x, /* frame width */
+ unsigned int dim_y, /* frame height */
+ unsigned int color /* fill color */
+ );
+
+/*
+ * graphics demo
+ * draw rectangles using pseudorandom number generator
+ * (see http://www.embedded.com/columns/technicalinsights/20900500)
+ */
+unsigned int rprime = 9972;
+static unsigned int r;
+static unsigned int Y;
+
+unsigned int prng(unsigned int max)
+{
+ if (r == 0 || r == 1 || r == -1)
+ r = rprime; /* keep from getting stuck */
+
+ r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
+ Y = (r >> 16) % max; /* choose upper bits and reduce */
+ return Y;
+}
+
+int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int color;
+ unsigned int x, y, dx, dy;
+
+ while (!ctrlc()) {
+ x = prng(1280 - 1);
+ y = prng(1024 - 1);
+ dx = prng(1280- x - 1);
+ dy = prng(1024 - y - 1);
+ color = prng(0x10000);
+ video_hw_rectfill(2, x, y, dx, dy, color);
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ gfxdemo, CFG_MAXARGS, 1, do_gfxdemo,
+ "gfxdemo - demo\n",
+ NULL
+ );
diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h
new file mode 100644
index 0000000..5c362e4
--- /dev/null
+++ b/board/esd/du440/du440.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDR0_USB0 0x0320 /* USB Control Register */
+
+#define CFG_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
+#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
+
+#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
+
+#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
+#define CFG_GPIO1_HWVER_SHIFT 4
+#define CFG_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
+#define CFG_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
+#define CFG_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
+#define CFG_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
+
+#define CPLD_VERSION_MASK 0x0f
+#define PWR_INT_FLAG 0x80
+#define PWR_RDY 0x10
+
+#define CPLD_IRQ (32+30)
+
+#define PCI_VENDOR_ID_ESDGMBH 0x12fe
+#define PCI_DEVICE_ID_DU440 0x0444
diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
new file mode 100644
index 0000000..4390b50
--- /dev/null
+++ b/board/esd/du440/init.S
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm-ppc/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ */
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entry for PCI IO */
+ tlbentry( CFG_PCI_IOBASE, SZ_64K, CFG_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entries for EBC: CPLD, DUMEM, DUIO */
+ tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_DUMEM_BASE, SZ_1M, CFG_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_DUIO_BASE, SZ_64K, CFG_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for NAND */
+ tlbentry( CFG_NAND0_ADDR, SZ_1K, CFG_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_NAND1_ADDR, SZ_1K, CFG_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /* TLB-entry PCI registers */
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ tlbtab_end
diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds
new file mode 100644
index 0000000..e140737
--- /dev/null
+++ b/board/esd/du440/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
--
1.5.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V3] ppc4xx: Complete DU440 board support
2008-01-16 11:20 ` Stefan Roese
@ 2008-01-16 12:00 ` Matthias Fuchs
2008-01-17 7:28 ` Stefan Roese
0 siblings, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-16 12:00 UTC (permalink / raw)
To: u-boot
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 3 +
include/configs/DU440.h | 435 +++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 440 insertions(+), 0 deletions(-)
create mode 100644 include/configs/DU440.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2ef2f5c..1996688 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -150,6 +150,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
DASA_SIM IOP480 (PPC401)
DP405 PPC405EP
DU405 PPC405GP
+ DU440 PPC440EPx
G2000 PPC405EP
HH405 PPC405EP
HUB405 PPC405EP
diff --git a/MAKEALL b/MAKEALL
index ebc5a22..0777dac 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -175,6 +175,7 @@ LIST_4xx=" \
DASA_SIM \
DP405 \
DU405 \
+ DU440 \
ebony \
ERIC \
EXBITGEN \
diff --git a/Makefile b/Makefile
index 1983ca0..7de2286 100644
--- a/Makefile
+++ b/Makefile
@@ -1191,6 +1191,9 @@ DP405_config: unconfig
DU405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx du405 esd
+DU440_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx du440 esd
+
ebony_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ebony amcc
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
new file mode 100644
index 0000000..001e8a8
--- /dev/null
+++ b/include/configs/DU440.h
@@ -0,0 +1,435 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * based on the Sequoia board configuration by
+ * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * DU440.h - configuration for esd DU440 board (PowerPC440EPx)
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_DU440 1 /* Board is esd DU440 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */
+#define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+#define CFG_PCI_IOBASE 0xe8000000
+
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+/* TODO: external clock oscillator will be removed */
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Video Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
+#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
+#define CFG_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
+#define CFG_CONSOLE_IS_IN_ENV
+#define CFG_ISA_IO CFG_PCI_IOBASE
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#if 0
+#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
+#endif
+#define CONFIG_DDR_ECC /* Use ECC when available */
+#define SPD_EEPROM_ADDRESS {0x50}
+#define CONFIG_PROG_SDRAM_TLB
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CONFIG_I2C_CMD_TREE 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+#define CFG_SPD_BUS_NUM 0
+#define IIC1_MCP3021_ADDR 0x4d
+#define IIC1_USB2507_ADDR 0x2c
+#ifdef CONFIG_I2C_MULTI_BUS
+#define CFG_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
+#endif
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR 0x54
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+
+#define CFG_EEPROM_WREN 1
+#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
+
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the TMP401
+ */
+#define CONFIG_DTT_SENSORS { 0, 1 }
+
+/*
+ * The PMC440 uses a TI TMP401 temperature sensor. This part
+ * is basically compatible to the ADM1021 that is supported
+ * by U-Boot.
+ *
+ * - i2c addr 0x4c
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
+ */
+#define CONFIG_DTT_ADM1021
+#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1338
+#define CFG_I2C_RTC_ADDR 0x68
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethrotate=no\0" \
+ "hostname=du440\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_self=run ramargs addip addtty optargs;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
+ "bootm\0" \
+ "rootpath=/tftpboot/du440/target_root_du440\0" \
+ "img=/tftpboot/du440/uImage\0" \
+ "kernel_addr=FFC00000\0" \
+ "ramdisk_addr=FFE00000\0" \
+ "initrd_high=30000000\0" \
+ "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
+ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
+ "cp.b 100000 FFFA0000 60000\0" \
+ ""
+#if 0
+#define CONFIG_BOOTCOMMAND "run flash_self"
+#endif
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#ifndef __ASSEMBLY__
+int du440_phy_addr(int devnum);
+#endif
+
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 128 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR du440_phy_addr(1)
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CFG_OHCI_BE_CONTROLLER
+
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
+#define CFG_USB_OHCI_SLOT_NAME "du440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_SUPPORT_VFAT
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+
+#define CFG_CPLD_BASE 0xC0000000
+#define CFG_CPLD_RANGE 0x00000010
+#define CFG_DUMEM_BASE 0xC0100000
+#define CFG_DUMEM_RANGE 0x00100000
+#define CFG_DUIO_BASE 0xC0200000
+#define CFG_DUIO_RANGE 0x00010000
+
+#define CFG_NAND0_CS 2 /* NAND chip connected to CSx */
+#define CFG_NAND1_CS 3 /* NAND chip connected to CSx */
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x04017200 /* mf test-only - disabled ready# */
+/* 0x03017200 = 90ns */ /* mf test-only - use 0x04017200 for 120ns */
+#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
+
+/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
+#define CFG_EBC_PB1AP 0x018003c0
+#define CFG_EBC_PB1CR (CFG_CPLD_BASE | 0x18000)
+
+/* Memory Bank 2 (NAND-FLASH) initialization */
+#define CFG_EBC_PB2AP 0x018003c0
+#define CFG_EBC_PB2CR (CFG_NAND0_ADDR | 0x1c000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x018003c0
+#define CFG_EBC_PB3CR (CFG_NAND1_ADDR | 0x1c000)
+
+/* Memory Bank 4 (DUMEM, 1MB) initialization */
+#define CFG_EBC_PB4AP 0x018053c0
+#define CFG_EBC_PB4CR (CFG_DUMEM_BASE | 0x18000)
+
+/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
+#define CFG_EBC_PB5AP 0x018053c0
+#define CFG_EBC_PB5CR (CFG_DUIO_BASE | 0x18000)
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE 2
+#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CFG_NAND_BASE_LIST {CFG_NAND0_ADDR + CFG_NAND0_CS, CFG_NAND1_ADDR + CFG_NAND1_CS}
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#if 0
+#define CONFIG_SHOW_ACTIVITY 1
+#endif
+
+#endif /* __CONFIG_H */
--
1.5.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
2008-01-14 10:35 ` Stefan Roese
2008-01-15 22:17 ` [U-Boot-Users] [PATCH] ppc4xx: Sequoia coding style cleanup and beautification Matthias Fuchs
@ 2008-01-16 12:05 ` Matthias Fuchs
1 sibling, 0 replies; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-16 12:05 UTC (permalink / raw)
To: u-boot
Stefan,
On Monday 14 January 2008 11:35, Stefan Roese wrote:
> On Monday 14 January 2008, Matthias Fuchs wrote:
> > I will update the DU440 patch tonight and also update the sequoia
> > sources in the same manner. So Stefan can lean back :-)
>
> /me leans back and keeps busy with other high priority stuff. :)
You should not lean back! There are a couple of coding style issue's
in makalu.c and kilauea.c (very long lines, comment format).
I cannot understand how these files made it into the repository:-)
Matthias
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V2] ppc4xx: Add DU440 board support
2008-01-16 11:52 ` Matthias Fuchs
@ 2008-01-16 15:23 ` Matthias Fuchs
0 siblings, 0 replies; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-16 15:23 UTC (permalink / raw)
To: u-boot
Hi Stefan,
my last posting was totally out of place and I didn't want to undermine your authority.
You are are doing an excellent job as the maintainer of your U-Boot subsystems.
Please keep on nagging on my (and others) patches!
Sorry.
Matthias
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V3] ppc4xx: Add DU440 board support
2008-01-16 11:59 ` [U-Boot-Users] [PATCH V3] " Matthias Fuchs
@ 2008-01-17 7:25 ` Stefan Roese
2008-01-17 9:52 ` [U-Boot-Users] [PATCH V4] " Matthias Fuchs
0 siblings, 1 reply; 24+ messages in thread
From: Stefan Roese @ 2008-01-17 7:25 UTC (permalink / raw)
To: u-boot
On Wednesday 16 January 2008, Matthias Fuchs wrote:
> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Please find some comments below.
> +++ b/board/esd/du440/du440.c
> @@ -0,0 +1,1018 @@
> +/*
<snip>
> +/*
> + * pci_pre_init
> + *
> + * This routine is called just prior to registering the hose and gives
> + * the board the opportunity to check things. Returning a value of zero
> + * indicates that things are bad & PCI initialization should be aborted.
> + *
> + * Different boards may wish to customize the pci controller structure
> + * (add regions, override default access routines, etc) or perform
> + * certain pre-initialization actions.
> + */
> +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
CFG_PCI_PRE_INIT was removed some time ago (with your help btw).
Please remove this #ifdef.
Please fix and resubmit.
Thanks.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V3] ppc4xx: Complete DU440 board support
2008-01-16 12:00 ` [U-Boot-Users] [PATCH V3] " Matthias Fuchs
@ 2008-01-17 7:28 ` Stefan Roese
2008-01-17 9:53 ` [U-Boot-Users] [PATCH V4] " Matthias Fuchs
0 siblings, 1 reply; 24+ messages in thread
From: Stefan Roese @ 2008-01-17 7:28 UTC (permalink / raw)
To: u-boot
On Wednesday 16 January 2008, Matthias Fuchs wrote:
> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Comments below.
> ---
> MAINTAINERS | 1 +
> MAKEALL | 1 +
> Makefile | 3 +
> include/configs/DU440.h | 435 +++++++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 440 insertions(+), 0 deletions(-)
> create mode 100644 include/configs/DU440.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2ef2f5c..1996688 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -150,6 +150,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
> DASA_SIM IOP480 (PPC401)
> DP405 PPC405EP
> DU405 PPC405GP
> + DU440 PPC440EPx
> G2000 PPC405EP
> HH405 PPC405EP
> HUB405 PPC405EP
> diff --git a/MAKEALL b/MAKEALL
> index ebc5a22..0777dac 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -175,6 +175,7 @@ LIST_4xx=" \
> DASA_SIM \
> DP405 \
> DU405 \
> + DU440 \
> ebony \
> ERIC \
> EXBITGEN \
> diff --git a/Makefile b/Makefile
> index 1983ca0..7de2286 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1191,6 +1191,9 @@ DP405_config: unconfig
> DU405_config: unconfig
> @$(MKCONFIG) $(@:_config=) ppc ppc4xx du405 esd
>
> +DU440_config: unconfig
> + @$(MKCONFIG) $(@:_config=) ppc ppc4xx du440 esd
> +
> ebony_config: unconfig
> @$(MKCONFIG) $(@:_config=) ppc ppc4xx ebony amcc
>
> diff --git a/include/configs/DU440.h b/include/configs/DU440.h
> new file mode 100644
> index 0000000..001e8a8
> --- /dev/null
> +++ b/include/configs/DU440.h
> @@ -0,0 +1,435 @@
> +/*
> + * (C) Copyright 2008
> + * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
> + *
> + * based on the Sequoia board configuration by
> + * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/************************************************************************
> + * DU440.h - configuration for esd DU440 board (PowerPC440EPx)
> + ***********************************************************************/
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*-----------------------------------------------------------------------
> + * High Level Configuration Options
> + *----------------------------------------------------------------------*/
> +#define CONFIG_DU440 1 /* Board is esd DU440 */
> +#define CONFIG_440EPX 1 /* Specific PPC440EPx */
> +#define CONFIG_4xx 1 /* ... PPC4xx family */
> +#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
> +
> +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
> +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
> +#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
> +
> +/*-----------------------------------------------------------------------
> + * Base addresses -- Note these are effective addresses where the
> + * actual resources get mapped (not physical addresses)
> + *----------------------------------------------------------------------*/
> +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
> +#define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
> +
> +#define CFG_BOOT_BASE_ADDR 0xf0000000
> +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
> +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
> +#define CFG_MONITOR_BASE TEXT_BASE
> +#define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */
> +#define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */
> +#define CFG_OCM_BASE 0xe0010000 /* ocm */
> +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
> +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
> +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
> +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
> +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
> +#define CFG_PCI_IOBASE 0xe8000000
> +
> +
> +/* Don't change either of these */
> +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
> +
> +#define CFG_USB2D0_BASE 0xe0000100
> +#define CFG_USB_DEVICE 0xe0000000
> +#define CFG_USB_HOST 0xe0000400
> +
> +/*-----------------------------------------------------------------------
> + * Initial RAM & stack pointer
> + *----------------------------------------------------------------------*/
> +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
> +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
> +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
> +
> +#define CFG_INIT_RAM_END (4 << 10)
> +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
> +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
> +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
> +
> +/*-----------------------------------------------------------------------
> + * Serial Port
> + *----------------------------------------------------------------------*/
> +/* TODO: external clock oscillator will be removed */
> +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SERIAL_MULTI 1
> +#undef CONFIG_UART1_CONSOLE
> +
> +#define CFG_BAUDRATE_TABLE \
> + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
> +
> +/*-----------------------------------------------------------------------
> + * Video Port
> + *----------------------------------------------------------------------*/
> +#define CONFIG_VIDEO
> +#define CONFIG_VIDEO_SMI_LYNXEM
> +#define CONFIG_CFB_CONSOLE
> +#define CONFIG_VIDEO_LOGO
> +#define CONFIG_VGA_AS_SINGLE_DEVICE
> +#define CONFIG_SPLASH_SCREEN
> +#define CONFIG_SPLASH_SCREEN_ALIGN
> +#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
> +#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
> +#define CFG_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
> +#define CFG_CONSOLE_IS_IN_ENV
> +#define CFG_ISA_IO CFG_PCI_IOBASE
> +
> +/*-----------------------------------------------------------------------
> + * Environment
> + *----------------------------------------------------------------------*/
> +#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
> +
> +/*-----------------------------------------------------------------------
> + * FLASH related
> + *----------------------------------------------------------------------*/
> +#define CFG_FLASH_CFI /* The flash is CFI compatible */
> +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
> +
> +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
> +
> +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
> +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
> +
> +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
> +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
> +
> +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
> +/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
> +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
> +
> +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
> +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
> +
> +#ifdef CFG_ENV_IS_IN_FLASH
> +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
> +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
> +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
> +
> +/* Address and size of Redundant Environment Sector */
> +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
> +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
> +#endif
> +
> +#ifdef CFG_ENV_IS_IN_EEPROM
> +#define CFG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
> +#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars*/
> +#endif
> +
> +/*-----------------------------------------------------------------------
> + * DDR SDRAM
> + *----------------------------------------------------------------------*/
> +#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
> +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
> +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
> +#if 0
> +#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
> +#endif
> +#define CONFIG_DDR_ECC /* Use ECC when available */
> +#define SPD_EEPROM_ADDRESS {0x50}
> +#define CONFIG_PROG_SDRAM_TLB
> +
> +/*-----------------------------------------------------------------------
> + * I2C
> + *----------------------------------------------------------------------*/
> +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
> +#undef CONFIG_SOFT_I2C /* I2C bit-banged */
> +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
> +#define CFG_I2C_SLAVE 0x7F
> +#define CONFIG_I2C_CMD_TREE 1
> +#define CONFIG_I2C_MULTI_BUS 1
> +
> +#define CFG_SPD_BUS_NUM 0
> +#define IIC1_MCP3021_ADDR 0x4d
> +#define IIC1_USB2507_ADDR 0x2c
> +#ifdef CONFIG_I2C_MULTI_BUS
> +#define CFG_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
> +#endif
> +#define CFG_I2C_MULTI_EEPROMS
> +#define CFG_I2C_EEPROM_ADDR 0x54
> +#define CFG_I2C_EEPROM_ADDR_LEN 2
> +#define CFG_EEPROM_PAGE_WRITE_ENABLE
> +#define CFG_EEPROM_PAGE_WRITE_BITS 5
> +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
> +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
> +
> +#define CFG_EEPROM_WREN 1
> +#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
> +
> +/*
> + * standard dtt sensor configuration - bottom bit will determine local or
> + * remote sensor of the TMP401
> + */
> +#define CONFIG_DTT_SENSORS { 0, 1 }
> +
> +/*
> + * The PMC440 uses a TI TMP401 temperature sensor. This part
> + * is basically compatible to the ADM1021 that is supported
> + * by U-Boot.
> + *
> + * - i2c addr 0x4c
> + * - conversion rate 0x02 = 0.25 conversions/second
> + * - ALERT ouput disabled
> + * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
> + * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
> + */
> +#define CONFIG_DTT_ADM1021
> +#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
> +
> +/*-----------------------------------------------------------------------
> + * RTC stuff
> + *-----------------------------------------------------------------------
> + */
> +#define CONFIG_RTC_DS1338
> +#define CFG_I2C_RTC_ADDR 0x68
> +
> +#undef CONFIG_BOOTARGS
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "netdev=eth0\0" \
> + "ethrotate=no\0" \
> + "hostname=du440\0" \
> + "nfsargs=setenv bootargs root=/dev/nfs rw " \
> + "nfsroot=${serverip}:${rootpath}\0" \
> + "ramargs=setenv bootargs root=/dev/ram rw\0" \
> + "addip=setenv bootargs ${bootargs} " \
> + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> + ":${hostname}:${netdev}:off panic=1\0" \
> + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
> + "flash_self=run ramargs addip addtty optargs;" \
> + "bootm ${kernel_addr} ${ramdisk_addr}\0" \
> + "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
> + "bootm\0" \
> + "rootpath=/tftpboot/du440/target_root_du440\0" \
> + "img=/tftpboot/du440/uImage\0" \
> + "kernel_addr=FFC00000\0" \
> + "ramdisk_addr=FFE00000\0" \
> + "initrd_high=30000000\0" \
> + "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
> + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
> + "cp.b 100000 FFFA0000 60000\0" \
> + ""
> +#if 0
> +#define CONFIG_BOOTCOMMAND "run flash_self"
> +#endif
> +
> +#define CONFIG_PREBOOT /* enable preboot variable */
> +
> +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
> +
> +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> +
> +#ifndef __ASSEMBLY__
> +int du440_phy_addr(int devnum);
> +#endif
> +
> +#define CONFIG_IBM_EMAC4_V4 1
> +#define CONFIG_MII 1 /* MII PHY management */
> +#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address, See schematics */
> +
> +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
> +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
> +
> +#define CONFIG_HAS_ETH0
> +#define CFG_RX_ETH_BUFFER 128 /* Number of ethernet rx buffers & descriptors */
> +
> +#define CONFIG_NET_MULTI 1
> +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
> +#define CONFIG_PHY1_ADDR du440_phy_addr(1)
> +
> +/* USB */
> +#define CONFIG_USB_OHCI_NEW
> +#define CONFIG_USB_STORAGE
> +#define CFG_OHCI_BE_CONTROLLER
> +
> +#define CFG_USB_OHCI_CPU_INIT 1
> +#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
> +#define CFG_USB_OHCI_SLOT_NAME "du440"
> +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
> +
> +/* Comment this out to enable USB 1.1 device */
> +#define USB_2_0_DEVICE
> +
> +/* Partitions */
> +#define CONFIG_MAC_PARTITION
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_ISO_PARTITION
> +
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_BSP
> +#define CONFIG_CMD_DATE
> +#define CONFIG_CMD_ASKENV
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_DTT
> +#define CONFIG_CMD_DIAG
> +#define CONFIG_CMD_EEPROM
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_IRQ
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NAND
> +#define CONFIG_CMD_NET
> +#define CONFIG_CMD_NFS
> +#define CONFIG_CMD_PCI
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_USB
> +#define CONFIG_CMD_REGINFO
> +#define CONFIG_CMD_SDRAM
> +
> +#define CONFIG_SUPPORT_VFAT
> +
> +/*-----------------------------------------------------------------------
> + * Miscellaneous configurable options
> + *----------------------------------------------------------------------*/
> +#define CFG_LONGHELP /* undef to save memory */
> +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
> +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
> +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
> +#else
> +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
> +#endif
> +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
> +#define CFG_MAXARGS 16 /* max number of command args */
> +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
> +
> +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
> +#define CFG_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
> +
> +#define CFG_LOAD_ADDR 0x100000 /* default load address */
> +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
> +
> +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
> +
> +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
> +#define CONFIG_LOOPW 1 /* enable loopw command */
> +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
> +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
> +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
> +
> +#define CONFIG_AUTOBOOT_KEYED 1
> +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
> +#define CONFIG_AUTOBOOT_DELAY_STR "d"
> +#define CONFIG_AUTOBOOT_STOP_STR " "
> +
> +/*-----------------------------------------------------------------------
> + * PCI stuff
> + *----------------------------------------------------------------------*/
> +/* General PCI */
> +#define CONFIG_PCI /* include pci support */
> +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
> +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
> +
> +/* Board-specific PCI */
> +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
Isn't necessary anymore. Please remove.
> +#define CFG_PCI_TARGET_INIT
> +#define CFG_PCI_MASTER_INIT
> +
> +/*
> + * For booting Linux, the board info and command line data
> + * have to be in the first 8 MB of memory, since this is
> + * the maximum mapped by the Linux kernel during initialization.
> + */
> +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
> +
> +/*-----------------------------------------------------------------------
> + * External Bus Controller (EBC) Setup
> + *----------------------------------------------------------------------*/
> +#define CFG_FLASH CFG_FLASH_BASE
> +
> +#define CFG_CPLD_BASE 0xC0000000
> +#define CFG_CPLD_RANGE 0x00000010
> +#define CFG_DUMEM_BASE 0xC0100000
> +#define CFG_DUMEM_RANGE 0x00100000
> +#define CFG_DUIO_BASE 0xC0200000
> +#define CFG_DUIO_RANGE 0x00010000
> +
> +#define CFG_NAND0_CS 2 /* NAND chip connected to CSx */
> +#define CFG_NAND1_CS 3 /* NAND chip connected to CSx */
> +/* Memory Bank 0 (NOR-FLASH) initialization */
> +#define CFG_EBC_PB0AP 0x04017200 /* mf test-only - disabled ready# */
> +/* 0x03017200 = 90ns */ /* mf test-only - use 0x04017200 for 120ns */
> +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
> +
> +/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
> +#define CFG_EBC_PB1AP 0x018003c0
> +#define CFG_EBC_PB1CR (CFG_CPLD_BASE | 0x18000)
> +
> +/* Memory Bank 2 (NAND-FLASH) initialization */
> +#define CFG_EBC_PB2AP 0x018003c0
> +#define CFG_EBC_PB2CR (CFG_NAND0_ADDR | 0x1c000)
> +
> +/* Memory Bank 3 (NAND-FLASH) initialization */
> +#define CFG_EBC_PB3AP 0x018003c0
> +#define CFG_EBC_PB3CR (CFG_NAND1_ADDR | 0x1c000)
> +
> +/* Memory Bank 4 (DUMEM, 1MB) initialization */
> +#define CFG_EBC_PB4AP 0x018053c0
> +#define CFG_EBC_PB4CR (CFG_DUMEM_BASE | 0x18000)
> +
> +/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
> +#define CFG_EBC_PB5AP 0x018053c0
> +#define CFG_EBC_PB5CR (CFG_DUIO_BASE | 0x18000)
> +
> +/*-----------------------------------------------------------------------
> + * NAND FLASH
> + *----------------------------------------------------------------------*/
> +#define CFG_MAX_NAND_DEVICE 2
> +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
> +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
> +#define CFG_NAND_BASE_LIST {CFG_NAND0_ADDR + CFG_NAND0_CS, CFG_NAND1_ADDR + CFG_NAND1_CS}
> +
> +/*
> + * Internal Definitions
> + *
> + * Boot Flags
> + */
> +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
> +#define BOOTFLAG_WARM 0x02 /* Software reboot */
> +
> +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
Please fix and resubmit.
Thanks.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V4] ppc4xx: Add DU440 board support
2008-01-17 7:25 ` Stefan Roese
@ 2008-01-17 9:52 ` Matthias Fuchs
2008-01-17 10:40 ` Stefan Roese
0 siblings, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-17 9:52 UTC (permalink / raw)
To: u-boot
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
board/esd/du440/Makefile | 51 +++
board/esd/du440/config.mk | 37 ++
board/esd/du440/du440.c | 1018 ++++++++++++++++++++++++++++++++++++++++++++
board/esd/du440/du440.h | 42 ++
board/esd/du440/init.S | 81 ++++
board/esd/du440/u-boot.lds | 145 +++++++
6 files changed, 1374 insertions(+), 0 deletions(-)
create mode 100644 board/esd/du440/Makefile
create mode 100644 board/esd/du440/config.mk
create mode 100644 board/esd/du440/du440.c
create mode 100644 board/esd/du440/du440.h
create mode 100644 board/esd/du440/init.S
create mode 100644 board/esd/du440/u-boot.lds
diff --git a/board/esd/du440/Makefile b/board/esd/du440/Makefile
new file mode 100644
index 0000000..e996a0a
--- /dev/null
+++ b/board/esd/du440/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esd/du440/config.mk b/board/esd/du440/config.mk
new file mode 100644
index 0000000..5164334
--- /dev/null
+++ b/board/esd/du440/config.mk
@@ -0,0 +1,37 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
new file mode 100644
index 0000000..ceb128c
--- /dev/null
+++ b/board/esd/du440/du440.c
@@ -0,0 +1,1018 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <i2c.h>
+#include <ppc440.h>
+#include "du440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern ulong flash_get_size (ulong base, int banknum);
+
+int usbhub_init(void);
+int dvi_init(void);
+int eeprom_write_enable (unsigned dev_addr, int state);
+int board_revision(void);
+
+static int du440_post_errors;
+
+int board_early_init_f(void)
+{
+ u32 sdr0_cust0;
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, 0xb8400000);
+
+ /*
+ * Setup the GPIO pins
+ */
+ out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_OSRL, 0x50055400);
+ out_be32((void*)GPIO0_OSRH, 0x550050aa);
+ out_be32((void*)GPIO0_TSRL, 0x50055400);
+ out_be32((void*)GPIO0_TSRH, 0x55005000);
+ out_be32((void*)GPIO0_ISR1L, 0x50000000);
+ out_be32((void*)GPIO0_ISR1H, 0x00000000);
+ out_be32((void*)GPIO0_ISR2L, 0x00000000);
+ out_be32((void*)GPIO0_ISR2H, 0x00000100);
+ out_be32((void*)GPIO0_ISR3L, 0x00000000);
+ out_be32((void*)GPIO0_ISR3H, 0x00000000);
+
+ out_be32((void*)GPIO1_OR, 0x00000000);
+ out_be32((void*)GPIO1_TCR, 0xc2000000 |
+ CFG_GPIO1_IORSTN |
+ CFG_GPIO1_LEDUSR1 |
+ CFG_GPIO1_LEDUSR2 |
+ CFG_GPIO1_LEDPOST |
+ CFG_GPIO1_LEDDU);
+ out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
+
+ out_be32((void*)GPIO1_OSRL, 0x5c280000);
+ out_be32((void*)GPIO1_OSRH, 0x00000000);
+ out_be32((void*)GPIO1_TSRL, 0x0c000000);
+ out_be32((void*)GPIO1_TSRH, 0x00000000);
+ out_be32((void*)GPIO1_ISR1L, 0x00005550);
+ out_be32((void*)GPIO1_ISR1H, 0x00000000);
+ out_be32((void*)GPIO1_ISR2L, 0x00050000);
+ out_be32((void*)GPIO1_ISR2H, 0x00000000);
+ out_be32((void*)GPIO1_ISR3L, 0x01400000);
+ out_be32((void*)GPIO1_ISR3H, 0x00000000);
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ /*
+ * UIC1:
+ * bit30: ext. Irq 1: PLD : int 32+30
+ */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xfffffffd);
+ mtdcr(uic1tr, 0x00000000);
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ /*
+ * UIC2
+ * bit3: ext. Irq 2: DCF77 : int 64+3
+ */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+
+ /* setup EMAC bridge interface */
+ if (board_revision() == 0) {
+ /* 1 x MII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_1_2;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_1_2;
+ } else {
+ /* 2 x SMII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_6;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_6;
+ }
+
+ /* enable 2nd IIC */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* PCI arbiter enabled */
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg);
+
+ /* setup NAND FLASH */
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ (0x80000000 >> (28 + CFG_NAND0_CS)) |
+ (0x80000000 >> (28 + CFG_NAND1_CS));
+ mtsdr(SDR0_CUST0, sdr0_cust0);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val = 0;
+ u32 reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ int i, j;
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(ebccfga, pb0cr);
+ mtdcr(ebccfgd, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /*
+ * USB suff...
+ */
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+ /* An 8-bit/60MHz interface is the only possible alternative
+ when connecting the Device to the PHY */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+ /* To enable the USB 2.0 Device function through the UTMI interface */
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /* clear resets */
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy)\n");
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
+ mtdcr(plb4_acr, reg);
+
+ /*
+ * release IO-RST#
+ * We have to wait at least 560ms until we may call usbhub_init
+ */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN);
+
+ /*
+ * flash USR1/2 LEDs (600ms)
+ * This results in the necessary delay from IORST# until
+ * calling usbhub_init will succeed
+ */
+ for (j = 0; j < 3; j++) {
+ out_be32((void*)GPIO1_OR,
+ (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR2) |
+ CFG_GPIO1_LEDUSR1);
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+
+ out_be32((void*)GPIO1_OR,
+ (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR1) |
+ CFG_GPIO1_LEDUSR2);
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+ }
+
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
+ ~(CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2));
+
+ if (usbhub_init())
+ du440_post_errors++;
+
+ if (dvi_init())
+ du440_post_errors++;
+
+ return 0;
+}
+
+int pld_revision(void)
+{
+ out8(CFG_CPLD_BASE, 0x00);
+ return (int)(in8(CFG_CPLD_BASE) & CPLD_VERSION_MASK);
+}
+
+int board_revision(void)
+{
+ int rpins = (int)((in_be32((void*)GPIO1_IR) & CFG_GPIO1_HWVER_MASK)
+ >> CFG_GPIO1_HWVER_SHIFT);
+
+ return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
+ ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
+}
+
+#if defined(CONFIG_SHOW_ACTIVITY)
+void board_show_activity (ulong timestamp)
+{
+ if ((timestamp % 100) == 0)
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) ^ CFG_GPIO1_LEDUSR1);
+}
+
+void show_activity(int arg)
+{
+}
+#endif /* CONFIG_SHOW_ACTIVITY */
+
+int du440_phy_addr(int devnum)
+{
+ if (board_revision() == 0)
+ return devnum;
+
+ return devnum + 1;
+}
+
+int checkboard(void)
+{
+ char serno[32];
+
+ puts("Board: DU440");
+
+ if (getenv_r("serial#", serno, sizeof(serno)) > 0) {
+ puts(", serial# ");
+ puts(serno);
+ }
+
+ printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
+ board_revision(), pld_revision());
+ return (0);
+}
+
+/*
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long addr;
+
+ /*
+ * Set priority for all PLB3 devices to 0.
+ * Set PLB3 arbiter to fair mode.
+ */
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*
+ * Set priority for all PLB4 devices to 0.
+ */
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*
+ * Set Nebula PLB4 arbiter to fair mode.
+ */
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*
+ * Set up Direct MMIO registers
+ */
+ /*
+ * PowerPC440EPX PCI Master configuration.
+ * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ * PLB address 0xA0000000-0xDFFFFFFF
+ * ==> PCI address 0xA0000000-0xDFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ * Make this region non-prefetchable.
+ */
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
+ /* and enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
+ /* and enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*
+ * Set up Configuration registers
+ */
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ PCI_VENDOR_ID_ESDGMBH);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
+
+ pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*
+ * Write the PowerPC440 EP PCI Configuration regs.
+ * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ */
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* always configured as host. */
+ return (1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+int last_stage_init(void)
+{
+ int e, i;
+
+ /* everyting is ok: turn on POST-LED */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+
+ /* slowly blink on errors and finally keep LED off */
+ for (e = 0; e < du440_post_errors; e++) {
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDPOST);
+
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_I2C_MULTI_BUS)
+/*
+ * read field strength from I2C ADC
+ */
+int dcf77_status(void)
+{
+ unsigned int oldbus;
+ uchar u[2];
+ int mv;
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(1);
+
+ if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
+ I2C_SET_BUS(oldbus);
+ return -1;
+ }
+
+ mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
+
+ I2C_SET_BUS(oldbus);
+ return mv;
+}
+
+int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int mv;
+ u32 pin, pinold;
+ unsigned long long t1, t2;
+ bd_t *bd = gd->bd;
+
+ printf("DCF77: ");
+ mv = dcf77_status();
+ if (mv > 0)
+ printf("signal=%d mV\n", mv);
+ else
+ printf("ERROR - no signal\n");
+
+ t1 = t2 = 0;
+ pinold = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+ while (!ctrlc()) {
+ pin = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+ if (pin && !pinold) { /* bit start */
+ t1 = get_ticks();
+ if (t2 && ((unsigned int)(t1 - t2) /
+ (bd->bi_procfreq / 1000) >= 1800))
+ printf("Start of minute\n");
+
+ t2 = t1;
+ }
+ if (t1 && !pin && pinold) { /* bit end */
+ printf("%5d\n", (unsigned int)(get_ticks() - t1) /
+ (bd->bi_procfreq / 1000));
+ }
+ pinold = pin;
+ }
+
+ printf("Abort\n");
+ return 0;
+}
+U_BOOT_CMD(
+ dcf77, 1, 1, do_dcf77,
+ "dcf77 - Check DCF77 receiver\n",
+ NULL
+ );
+
+/*
+ * initialize USB hub via I2C1
+ */
+int usbhub_init(void)
+{
+ int reg;
+ int ret = 0;
+ unsigned int oldbus;
+ uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
+ 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
+ 0x32};
+ uchar stcd;
+
+ printf("Hub: ");
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(1);
+
+ for (reg = 0; reg < sizeof(u); reg++)
+ if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
+ ret = -1;
+ break;
+ }
+
+ if (ret == 0) {
+ stcd = 0x03;
+ if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
+ ret = -1;
+ }
+
+ if (ret == 0)
+ printf("initialized\n");
+ else
+ printf("failed - cannot initialize USB hub\n");
+
+ I2C_SET_BUS(oldbus);
+ return ret;
+}
+
+int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ usbhub_init();
+ return 0;
+}
+U_BOOT_CMD(
+ hubinit, 1, 1, do_hubinit,
+ "hubinit - Initialize USB hub\n",
+ NULL
+ );
+#endif /* CONFIG_I2C_MULTI_BUS */
+
+#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int boot_eeprom_write (unsigned dev_addr,
+ unsigned offset,
+ uchar *buffer,
+ unsigned cnt)
+{
+ unsigned end = offset + cnt;
+ unsigned blk_off;
+ int rcode = 0;
+
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 1);
+#endif
+ /*
+ * Write data until done or would cross a write page boundary.
+ * We must write the address again when changing pages
+ * because the address counter only increments within a page.
+ */
+
+ while (offset < end) {
+ unsigned alen, len;
+ unsigned maxlen;
+
+ uchar addr[2];
+
+ blk_off = offset & 0xFF; /* block offset */
+
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
+ addr[0] |= dev_addr; /* insert device address */
+
+ len = end - offset;
+
+ /*
+ * For a FRAM device there is no limit on the number of the
+ * bytes that can be ccessed with the single read or write
+ * operation.
+ */
+#if defined(CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+
+#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+ maxlen = BOOT_EEPROM_PAGE_SIZE -
+ BOOT_EEPROM_PAGE_OFFSET(blk_off);
+#else
+ maxlen = 0x100 - blk_off;
+#endif
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
+
+ if (len > maxlen)
+ len = maxlen;
+
+ if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
+ rcode = 1;
+
+ buffer += len;
+ offset += len;
+
+#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+ }
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 0);
+#endif
+ return rcode;
+}
+
+int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong sdsdp[4];
+
+ if (argc > 1) {
+ if (!strcmp(argv[1], "533")) {
+ printf("Bootstrapping for 533MHz\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+ sdsdp[1] = 0x095fa030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "533-66")) {
+ printf("Bootstrapping for 533MHz (66MHz PCI)\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
+ sdsdp[1] = 0x0957a030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "667")) {
+ printf("Bootstrapping for 667MHz\n");
+ sdsdp[0] = 0x8778a256;
+ /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
+ sdsdp[1] = 0x0947a030;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
+ * -> not working when overclocking 533MHz chips
+ * -> untested on 667MHz chips */
+ /* sdsdp[1]=0x095fa030; */
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ }
+ } else {
+ printf("Bootstrapping for 533MHz (default)\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+ sdsdp[1] = 0x095fa030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ }
+
+ printf("Writing boot EEPROM ...\n");
+ if (boot_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
+ 0, (uchar*)sdsdp, 16) != 0)
+ printf("boot_eeprom_write failed\n");
+ else
+ printf("done (dump via 'i2c md 52 0.1 10')\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ sbe, 2, 0, do_setup_boot_eeprom,
+ "sbe - setup boot eeprom\n",
+ NULL
+ );
+
+#if defined(CFG_EEPROM_WREN)
+/*
+ * Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
+ (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr))
+ return -1;
+ else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CFG_GPIO0_EP_EEP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CFG_GPIO0_EP_EEP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void*)GPIO0_OR) &
+ CFG_GPIO0_EP_EEP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0)
+ puts ("Query of write access state failed.\n");
+ else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0)
+ puts ("Setup of write access state failed.\n");
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+static int got_pldirq;
+
+static int pld_interrupt(u32 arg)
+{
+ int rc = -1; /* not for us */
+ u8 status = in8(CFG_CPLD_BASE);
+
+ /* check for PLD interrupt */
+ if (status & PWR_INT_FLAG) {
+ /* reset this int */
+ out8(CFG_CPLD_BASE, 0);
+ rc = 0;
+ got_pldirq = 1; /* trigger backend */
+ }
+
+ return rc;
+}
+
+int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ got_pldirq = 0;
+
+ /* clear any pending interrupt */
+ out8(CFG_CPLD_BASE, 0);
+
+ irq_install_handler(CPLD_IRQ,
+ (interrupt_handler_t *)pld_interrupt, 0);
+
+ printf("Waiting ...\n");
+ while(!got_pldirq) {
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ break;
+ }
+ }
+ if (got_pldirq) {
+ printf("Got interrupt!\n");
+ printf("Power %sready!\n",
+ in8(CFG_CPLD_BASE) & PWR_RDY ? "":"NOT ");
+ }
+
+ irq_free_handler(CPLD_IRQ);
+ return 0;
+}
+U_BOOT_CMD(
+ wpi, 1, 1, do_waitpwrirq,
+ "wpi - Wait for power change interrupt\n",
+ NULL
+ );
+
+/*
+ * initialize DVI panellink transmitter
+ */
+int dvi_init(void)
+{
+ int i;
+ int ret = 0;
+ unsigned int oldbus;
+ uchar u[] = {0x08, 0x34,
+ 0x09, 0x20,
+ 0x0a, 0x90,
+ 0x0c, 0x89,
+ 0x08, 0x35};
+
+ printf("DVI: ");
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(0);
+
+ for (i = 0; i < sizeof(u); i += 2)
+ if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
+ ret = -1;
+ break;
+ }
+
+ if (ret == 0)
+ printf("initialized\n");
+ else
+ printf("failed - cannot initialize DVI transmitter\n");
+
+ I2C_SET_BUS(oldbus);
+ return ret;
+}
+
+int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ dvi_init();
+ return 0;
+}
+U_BOOT_CMD(
+ dviinit, 1, 1, do_dviinit,
+ "dviinit - Initialize DVI Panellink transmitter\n",
+ NULL
+ );
+
+/*
+ * TODO: 'time' command might be useful for others as well.
+ * Move to 'common' directory.
+ */
+int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long long start, end;
+ char c, cmd[CFG_CBSIZE];
+ char *p, *d = cmd;
+ int ret, i;
+ ulong us;
+
+ for (i = 1; i < argc; i++) {
+ p = argv[i];
+
+ if (i > 1)
+ *d++ = ' ';
+
+ while ((c = *p++) != '\0') {
+ *d++ = c;
+ }
+ }
+ *d = '\0';
+
+ start = get_ticks();
+ ret = run_command (cmd, 0);
+ end = get_ticks();
+
+ printf("ticks=%d\n", (ulong)(end - start));
+ us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
+ printf("usec=%d\n", us);
+
+ return ret;
+}
+U_BOOT_CMD(
+ time, CFG_MAXARGS, 1, do_time,
+ "time - run command and output execution time\n",
+ NULL
+ );
+
+extern void video_hw_rectfill (
+ unsigned int bpp, /* bytes per pixel */
+ unsigned int dst_x, /* dest pos x */
+ unsigned int dst_y, /* dest pos y */
+ unsigned int dim_x, /* frame width */
+ unsigned int dim_y, /* frame height */
+ unsigned int color /* fill color */
+ );
+
+/*
+ * graphics demo
+ * draw rectangles using pseudorandom number generator
+ * (see http://www.embedded.com/columns/technicalinsights/20900500)
+ */
+unsigned int rprime = 9972;
+static unsigned int r;
+static unsigned int Y;
+
+unsigned int prng(unsigned int max)
+{
+ if (r == 0 || r == 1 || r == -1)
+ r = rprime; /* keep from getting stuck */
+
+ r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
+ Y = (r >> 16) % max; /* choose upper bits and reduce */
+ return Y;
+}
+
+int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int color;
+ unsigned int x, y, dx, dy;
+
+ while (!ctrlc()) {
+ x = prng(1280 - 1);
+ y = prng(1024 - 1);
+ dx = prng(1280- x - 1);
+ dy = prng(1024 - y - 1);
+ color = prng(0x10000);
+ video_hw_rectfill(2, x, y, dx, dy, color);
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ gfxdemo, CFG_MAXARGS, 1, do_gfxdemo,
+ "gfxdemo - demo\n",
+ NULL
+ );
diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h
new file mode 100644
index 0000000..5c362e4
--- /dev/null
+++ b/board/esd/du440/du440.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDR0_USB0 0x0320 /* USB Control Register */
+
+#define CFG_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
+#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
+
+#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
+
+#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
+#define CFG_GPIO1_HWVER_SHIFT 4
+#define CFG_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
+#define CFG_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
+#define CFG_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
+#define CFG_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
+
+#define CPLD_VERSION_MASK 0x0f
+#define PWR_INT_FLAG 0x80
+#define PWR_RDY 0x10
+
+#define CPLD_IRQ (32+30)
+
+#define PCI_VENDOR_ID_ESDGMBH 0x12fe
+#define PCI_DEVICE_ID_DU440 0x0444
diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
new file mode 100644
index 0000000..4390b50
--- /dev/null
+++ b/board/esd/du440/init.S
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm-ppc/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ */
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entry for PCI IO */
+ tlbentry( CFG_PCI_IOBASE, SZ_64K, CFG_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entries for EBC: CPLD, DUMEM, DUIO */
+ tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_DUMEM_BASE, SZ_1M, CFG_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_DUIO_BASE, SZ_64K, CFG_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for NAND */
+ tlbentry( CFG_NAND0_ADDR, SZ_1K, CFG_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_NAND1_ADDR, SZ_1K, CFG_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /* TLB-entry PCI registers */
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ tlbtab_end
diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds
new file mode 100644
index 0000000..e140737
--- /dev/null
+++ b/board/esd/du440/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
--
1.5.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V4] ppc4xx: Complete DU440 board support
2008-01-17 7:28 ` Stefan Roese
@ 2008-01-17 9:53 ` Matthias Fuchs
2008-01-17 10:41 ` Stefan Roese
0 siblings, 1 reply; 24+ messages in thread
From: Matthias Fuchs @ 2008-01-17 9:53 UTC (permalink / raw)
To: u-boot
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 3 +
include/configs/DU440.h | 438 +++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 443 insertions(+), 0 deletions(-)
create mode 100644 include/configs/DU440.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2ef2f5c..1996688 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -150,6 +150,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
DASA_SIM IOP480 (PPC401)
DP405 PPC405EP
DU405 PPC405GP
+ DU440 PPC440EPx
G2000 PPC405EP
HH405 PPC405EP
HUB405 PPC405EP
diff --git a/MAKEALL b/MAKEALL
index ebc5a22..0777dac 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -175,6 +175,7 @@ LIST_4xx=" \
DASA_SIM \
DP405 \
DU405 \
+ DU440 \
ebony \
ERIC \
EXBITGEN \
diff --git a/Makefile b/Makefile
index 1983ca0..7de2286 100644
--- a/Makefile
+++ b/Makefile
@@ -1191,6 +1191,9 @@ DP405_config: unconfig
DU405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx du405 esd
+DU440_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx du440 esd
+
ebony_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ebony amcc
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
new file mode 100644
index 0000000..4fb6921
--- /dev/null
+++ b/include/configs/DU440.h
@@ -0,0 +1,438 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com
+ *
+ * based on the Sequoia board configuration by
+ * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ **********************************************************************
+ * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
+ **********************************************************************
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_DU440 1 /* Board is esd DU440 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */
+#define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+#define CFG_PCI_IOBASE 0xe8000000
+
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+
+/*
+ * Initial RAM & stack pointer
+ */
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*
+ * Serial Port
+ */
+/* TODO: external clock oscillator will be removed */
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Video Port
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
+#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
+#define CFG_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
+#define CFG_CONSOLE_IS_IN_ENV
+#define CFG_ISA_IO CFG_PCI_IOBASE
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
+
+/*
+ * FLASH related
+ */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET 0 /* environment starts at */
+ /* the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
+#endif
+
+/*
+ * DDR SDRAM
+ */
+#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#if 0
+#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
+#endif
+#define CONFIG_DDR_ECC /* Use ECC when available */
+#define SPD_EEPROM_ADDRESS {0x50}
+#define CONFIG_PROG_SDRAM_TLB
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CONFIG_I2C_CMD_TREE 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+#define CFG_SPD_BUS_NUM 0
+#define IIC1_MCP3021_ADDR 0x4d
+#define IIC1_USB2507_ADDR 0x2c
+#ifdef CONFIG_I2C_MULTI_BUS
+#define CFG_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
+#endif
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR 0x54
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+
+#define CFG_EEPROM_WREN 1
+#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
+
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the TMP401
+ */
+#define CONFIG_DTT_SENSORS { 0, 1 }
+
+/*
+ * The PMC440 uses a TI TMP401 temperature sensor. This part
+ * is basically compatible to the ADM1021 that is supported
+ * by U-Boot.
+ *
+ * - i2c addr 0x4c
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
+ */
+#define CONFIG_DTT_ADM1021
+#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+
+/*
+ * RTC stuff
+ */
+#define CONFIG_RTC_DS1338
+#define CFG_I2C_RTC_ADDR 0x68
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethrotate=no\0" \
+ "hostname=du440\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_self=run ramargs addip addtty optargs;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
+ "bootm\0" \
+ "rootpath=/tftpboot/du440/target_root_du440\0" \
+ "img=/tftpboot/du440/uImage\0" \
+ "kernel_addr=FFC00000\0" \
+ "ramdisk_addr=FFE00000\0" \
+ "initrd_high=30000000\0" \
+ "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
+ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
+ "cp.b 100000 FFFA0000 60000\0" \
+ ""
+#if 0
+#define CONFIG_BOOTCOMMAND "run flash_self"
+#endif
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#ifndef __ASSEMBLY__
+int du440_phy_addr(int devnum);
+#endif
+
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE detection */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 128
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR du440_phy_addr(1)
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CFG_OHCI_BE_CONTROLLER
+
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
+#define CFG_USB_OHCI_SLOT_NAME "du440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * PCI stuff
+ */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define CFG_FLASH CFG_FLASH_BASE
+
+#define CFG_CPLD_BASE 0xC0000000
+#define CFG_CPLD_RANGE 0x00000010
+#define CFG_DUMEM_BASE 0xC0100000
+#define CFG_DUMEM_RANGE 0x00100000
+#define CFG_DUIO_BASE 0xC0200000
+#define CFG_DUIO_RANGE 0x00010000
+
+#define CFG_NAND0_CS 2 /* NAND chip connected to CSx */
+#define CFG_NAND1_CS 3 /* NAND chip connected to CSx */
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x04017200
+#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
+
+/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
+#define CFG_EBC_PB1AP 0x018003c0
+#define CFG_EBC_PB1CR (CFG_CPLD_BASE | 0x18000)
+
+/* Memory Bank 2 (NAND-FLASH) initialization */
+#define CFG_EBC_PB2AP 0x018003c0
+#define CFG_EBC_PB2CR (CFG_NAND0_ADDR | 0x1c000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x018003c0
+#define CFG_EBC_PB3CR (CFG_NAND1_ADDR | 0x1c000)
+
+/* Memory Bank 4 (DUMEM, 1MB) initialization */
+#define CFG_EBC_PB4AP 0x018053c0
+#define CFG_EBC_PB4CR (CFG_DUMEM_BASE | 0x18000)
+
+/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
+#define CFG_EBC_PB5AP 0x018053c0
+#define CFG_EBC_PB5CR (CFG_DUIO_BASE | 0x18000)
+
+/*
+ * NAND FLASH
+ */
+#define CFG_MAX_NAND_DEVICE 2
+#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CFG_NAND_BASE_LIST {CFG_NAND0_ADDR + CFG_NAND0_CS, \
+ CFG_NAND1_ADDR + CFG_NAND1_CS}
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#if 0
+#define CONFIG_SHOW_ACTIVITY 1
+#endif
+
+#endif /* __CONFIG_H */
--
1.5.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V4] ppc4xx: Add DU440 board support
2008-01-17 9:52 ` [U-Boot-Users] [PATCH V4] " Matthias Fuchs
@ 2008-01-17 10:40 ` Stefan Roese
0 siblings, 0 replies; 24+ messages in thread
From: Stefan Roese @ 2008-01-17 10:40 UTC (permalink / raw)
To: u-boot
On Thursday 17 January 2008, Matthias Fuchs wrote:
> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Applied, thanks.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot-Users] [PATCH V4] ppc4xx: Complete DU440 board support
2008-01-17 9:53 ` [U-Boot-Users] [PATCH V4] " Matthias Fuchs
@ 2008-01-17 10:41 ` Stefan Roese
0 siblings, 0 replies; 24+ messages in thread
From: Stefan Roese @ 2008-01-17 10:41 UTC (permalink / raw)
To: u-boot
On Thursday 17 January 2008, Matthias Fuchs wrote:
> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Applied, thanks.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2008-01-17 10:41 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-01-13 21:11 [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support Matthias Fuchs
2008-01-13 22:08 ` Wolfgang Denk
2008-01-14 8:58 ` Matthias Fuchs
2008-01-14 9:45 ` Wolfgang Denk
2008-01-14 10:05 ` Matthias Fuchs
2008-01-14 10:35 ` Stefan Roese
2008-01-15 22:17 ` [U-Boot-Users] [PATCH] ppc4xx: Sequoia coding style cleanup and beautification Matthias Fuchs
2008-01-16 7:31 ` Stefan Roese
2008-01-16 9:33 ` [U-Boot-Users] [PATCH V2] " Matthias Fuchs
2008-01-16 10:33 ` Stefan Roese
2008-01-16 12:05 ` [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support Matthias Fuchs
2008-01-16 10:47 ` [U-Boot-Users] [PATCH V2] " Matthias Fuchs
[not found] ` <200801161219.08916.sr@denx.de>
2008-01-16 11:52 ` Matthias Fuchs
2008-01-16 15:23 ` Matthias Fuchs
2008-01-16 11:59 ` [U-Boot-Users] [PATCH V3] " Matthias Fuchs
2008-01-17 7:25 ` Stefan Roese
2008-01-17 9:52 ` [U-Boot-Users] [PATCH V4] " Matthias Fuchs
2008-01-17 10:40 ` Stefan Roese
2008-01-16 10:47 ` [U-Boot-Users] [PATCH V2] ppc4xx: Complete " Matthias Fuchs
2008-01-16 11:20 ` Stefan Roese
2008-01-16 12:00 ` [U-Boot-Users] [PATCH V3] " Matthias Fuchs
2008-01-17 7:28 ` Stefan Roese
2008-01-17 9:53 ` [U-Boot-Users] [PATCH V4] " Matthias Fuchs
2008-01-17 10:41 ` Stefan Roese
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