From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stefan Roese <sr@denx.de>
Date: Sat, 2 Feb 2008 08:58:14 +0100
Subject: [U-Boot-Users] RFC: About clearing watchdog status on ppc4xx
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References: <2C7DE72B9BD00F44BAECA5B0CBB873950422EF@hermes.terascala.com>
Message-ID: <200802020858.15073.sr@denx.de>
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To: u-boot@lists.denx.de

Mike,

On Friday 01 February 2008, Mike Nuss wrote:
> The following line in cpu/ppc4xx/start.S:
>
>     mtspr    tsr,r1            /* clear all timer exception status */
>
> has the effect of clearing WRS, making it impossible for a watchdog device
> driver (such as Linux's booke-wdt) to later check those bits to determine
> whether a reset occurred. I assume the reason those bits are cleared by
> U-Boot is because they are undefined on poweron reset. However, it's
> possible to build a board with external logic to detect whether a poweron
> reset occurred, as suggested by AMCC's application note on the watchdog
> timer.
>
> We have built such a board. For now I have just commented out that line of
> code, and later on in Linux I check the external logic, which requires
> checking and setting GPIOs tied to a flip-flop. Obviously there is a better
> solution. I think it would make sense to add a CFG option to U-Boot that
> would have the following two effects:
>
> 1. Change that line so it clears all status except WRS
> 2. In the board-specific code, once the GPIO controller has been
> configured, check the flip flop there, and clear the bits if a poweron
> reset occurred. Then Linux (or any OS) can simply look at those bits and
> can depend on their contents being "as correct as possible" - on boards
> without the external logic, it will simply always read 0, as it does now,
> but on boards such as ours, it will reflect the actual status.
>
> Does this make sense? I can submit a patch.

Sure. Please go ahead. I'll probably comment in more details when you patch is 
available.

Thanks.

Best regards,
Stefan

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