[U-Boot-Users] [PATCH 1/3] ppc4xx: PPC405GPr add missing EIRR register

[Stefan Roese <sr@denx.de>]

On Monday 04 February 2008, Niklaus Giger wrote:
> > Why is 405GPr needed here? Is this register not available in 405GP?
>
> I found the following comments in the Migration guide for the PPC405GP ->
> PPC405GPr (PPC405GP_AN2023_405GPrMigration__v1_01.pdf).
>
> > The 405GPr provides the ability to add six external interrupts to the
> > seven already available on the 405GP. This is accomplished by logic that
> > allows routing any of the 24 GPIOs to six  previously unused Universal
> > Interrupt Controller (UIC) inputs. For those GPIOs that are shared with
> > other functions, the corresponding I/O must first be configured via
> > CPC0_CR0 to be a GPIO. Table 14 shows how the new GPIO to UIC External
> > Interrupt Routing Register (CPC0_EIRR) logically routes GPIO inputs used
> > as interrupts to the UIC.
>
> Therefore I concluded that it is very PPC405GPr specific. But I did not
> check all other PPC405 variants.

Yes, you seem to be right here. This *is* 405GPr specific. But I don't think 
it is worth adding this CONFIG_405GPr. Right now by setting CONFIG_405GP in 
your board config file, it should work correctly on boards with 405GP *and* 
405GPr. We shouldn't loose this "feature". So please add this define if 
CONFIG_405GP is defined. And add a comment that it is only valid for 405GPr.

Thanks.

Best regards,
Stefan

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