From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Sat, 9 Feb 2008 06:51:31 +0100 Subject: [U-Boot-Users] 440EPX is not booting from 1Gb/128MB NAND flash In-Reply-To: References: <200802080550.10933.sr@denx.de> Message-ID: <200802090651.31856.sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Nikhil, On Friday 08 February 2008, Nikhil Gautam wrote: > After some debugging using BDI, I found out that there are more then > one problem here. > > IPL loads the SPL correctly. And I can see that nand_boot( ) is > called. The first problem I found was that the nand_is_bad_block( ) is > returning true after a while. I think its treating empty blocks as bad > blocks. I know there are no bad blocks because I booted using the NOR > image and then checked the NAND flash. How did you define CFG_NAND_BAD_BLOCK_POS in your board config file? For 512 byte page devices this is "5" but for 2k devices it should be "0". For testing you could change nand_is_bad_block() to return always 0. > Secondly, the SPL is copying the u-boot image to ram incorrectly. By > this I mean, when I do the memory dump of RAM where U-boot image > should be loaded, only the first NAND page (2K) is copied correctly. > After that it's random or empty. > > The third problem is that in the board config file > #define CFG_NAND_U_BOOT_OFFS (16 << 10) > is incorrect for current U-boot. If you look at nand_boot.c > /* > * offs has to be aligned to a block address! > */ > block = CFG_NAND_U_BOOT_OFFS / CFG_NAND_BLOCK_SIZE; > > This is because this file copies sectors completely. For 2k page size > and 64 pages per block, The SPL is again copying the complete NAND > flash from address "0" to RAM. > > Changing this define to > #define CFG_NAND_U_BOOT_OFFS (128 << 10) > will not help because when u-boot is compiles, it pads the image > enough so that the U-Boot ram image is always located at 16K. Do you > know how can I change it to that my new U-boot ram image starts from > 128K offset. Sure. This is defined in the nand_spl config.mk file. For example Sequoia has here in nand_spl/board/amcc/sequoia/config.mk: # On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff, # in the last 4kBytes of memory space in cache. # We will copy this SPL into internal SRAM in start.S. So we set # TEXT_BASE to starting address in internal SRAM here. # TEXT_BASE = 0xE0013000 # PAD_TO used to generate a 16kByte binary needed for the combined image # -> PAD_TO = TEXT_BASE + 0x4000 PAD_TO = 0xE0017000 You need to change this PAD_TO accordingly. Hope this helps. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================