[U-Boot-Users] FPGA mess

[Stefan Roese <sr@denx.de>]

Andre,

On Wednesday 05 March 2008, Andre Schwarz wrote:
> you're listed as maintainer for the alpr board.

Correct. But I didn't use this board for quite some time.

> It's the only board that uses the ACEX1K.c file for FPGA loading...

Does it? To use this file you have to define CONFIG_FPGA_ACEX1K. I don't see 
it defined anywhere in the whole U-Boot tree. So perhaps this code is not 
used at all.

> I'm quite sure there are many boards with Altera FPGAs outside and can't
> believe they have all mounted
> platform flashes and therefore don't use u-boot for loading the FPGA.
> Nevertheless those board don't show up in the tree. Maybe they all keep
> their own patches like me ...

Maybe. I suggest you start pushing your code to change this situation. :)

> There are some points that doesn't seem to work out very well in general.
> This is where some questions come up (top->down) :
>
> common/cmd_fpga:
> In function do_fpga there's a used environment variable "fpgadata" that
> obviously stores the location of the bitstream.
> What sense does this make if the "data_size" parameter (=arg4) is _not_
> optional ?
> Instead the command "fpga load 0 0x..." leads to a load function with
> zero length.
> The user always has to supply all 4 args (load, nr, data, size).
> Of course the loading function could use the pre-defined bitstream size
> from the header or the device struct...

I have to admit that I don't understand what you are really asking here. 
Please ask more specific questions. Or send a patch to fix something that 
is "broken".

> common/altera.c
> What's that ACEX1K ? Isn't it a Cyclone chip and should use that interface
> ? Why does this need special treatment throughout the interface ?

I didn't introduce this file. Perhaps we should ask the author who committed 
this code.

> include/ACEX1K.h
> Obviously there are some confusions about the various file formats and
> sizes that can be output
> from Altera's SoPC Builder. Compression is also possible with
> de-compression on the fly during load ...
> Of course the defined file sizes should match a raw bit file that
> represents the true size of the device.
>
> Why is ACEX1K and Cyclone not merged ?

No idea. If you have some fixes, please send patches.

> Does _any_ real board use the Altera path ? scanning the config files
> ... no.

alpr seems to use the cyclone2.c code.

> CYC2_ps_load in common/cyclon2.c the nCONFIG pin is never de-asserted
> during preparation. This code can't work.

No idea. I have to admit, that I didn't implement the FPGA booting on this 
board. But it seems to work fine.

> Is there any interest in getting this fixed ?

Sure.

> What about Liberty's Stratix code ? It's living and working !

Sorry, but I have no clue what "Liberty's Stratix code" is.

Best regards,
Stefan

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