[U-Boot-Users] [PATCH 3/7] 83xx: serdes setup routines

[U-Boot-Users] [PATCH 3/7] 83xx: serdes setup routines

[Anton Vorontsov]

This patch adds few routines to configure serdes on 837x targets.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 cpu/mpc83xx/Makefile         |    1 +
 cpu/mpc83xx/serdes.c         |  156 ++++++++++++++++++++++++++++++++++++++++++
 include/asm-ppc/fsl_serdes.h |   25 +++++++
 3 files changed, 182 insertions(+), 0 deletions(-)
 create mode 100644 cpu/mpc83xx/serdes.c
 create mode 100644 include/asm-ppc/fsl_serdes.h

diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
index 7ad7e3e..6b6b027 100644
--- a/cpu/mpc83xx/Makefile
+++ b/cpu/mpc83xx/Makefile
@@ -39,6 +39,7 @@ COBJS-y += ecc.o
 COBJS-$(CONFIG_QE) += qe_io.o
 COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+COBJS-$(CONFIG_FSL_SERDES) += serdes.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c
new file mode 100644
index 0000000..a1dea16
--- /dev/null
+++ b/cpu/mpc83xx/serdes.c
@@ -0,0 +1,156 @@
+/*
+ * Freescale SerDes initialization routine
+ *
+ * Copyright (C) 2007 Freescale Semicondutor, Inc. All rights reserved.
+ * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved.
+ *
+ * Author: Li Yang <leoli@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+
+/* SerDes registers */
+#define FSL_SRDSCR0_OFFS		0x0
+#define FSL_SRDSCR0_DPP_1V2		0x00008800
+#define FSL_SRDSCR1_OFFS		0x4
+#define FSL_SRDSCR1_PLLBW		0x00000040
+#define FSL_SRDSCR2_OFFS		0x8
+#define FSL_SRDSCR2_VDD_1V2		0x00800000
+#define FSL_SRDSCR2_SEIC_MASK		0x00001c1c
+#define FSL_SRDSCR2_SEIC_SATA		0x00001414
+#define FSL_SRDSCR2_SEIC_PEX		0x00001010
+#define FSL_SRDSCR2_SEIC_SGMII		0x00000101
+#define FSL_SRDSCR3_OFFS		0xc
+#define FSL_SRDSCR3_KFR_SATA		0x10100000
+#define FSL_SRDSCR3_KPH_SATA		0x04040000
+#define FSL_SRDSCR3_SDFM_SATA_PEX	0x01010000
+#define FSL_SRDSCR3_SDTXL_SATA		0x00000505
+#define FSL_SRDSCR4_OFFS		0x10
+#define FSL_SRDSCR4_PROT_SATA		0x00000808
+#define FSL_SRDSCR4_PROT_PEX		0x00000101
+#define FSL_SRDSCR4_PROT_SGMII		0x00000505
+#define FSL_SRDSCR4_PLANE_X2		0x01000000
+#define FSL_SRDSRSTCTL_OFFS		0x20
+#define FSL_SRDSRSTCTL_RST		0x80000000
+#define FSL_SRDSRSTCTL_SATA_RESET	0xf
+
+static void setup_serdes(void *regs, char proto, char rfcks, char vdd)
+{
+	u32 tmp;
+
+	/* 1.0V corevdd */
+	if (vdd) {
+		/* DPPE/DPPA = 0 */
+		tmp = in_be32(regs + FSL_SRDSCR0_OFFS);
+		tmp &= ~FSL_SRDSCR0_DPP_1V2;
+		out_be32(regs + FSL_SRDSCR0_OFFS, tmp);
+
+		/* VDD = 0 */
+		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+		tmp &= ~FSL_SRDSCR2_VDD_1V2;
+		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+	}
+
+	/* protocol specific configuration */
+	switch (proto) {
+	case FSL_SERDES_PROTO_SATA:
+		/* Set and clear reset bits */
+		tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
+		tmp |= FSL_SRDSRSTCTL_SATA_RESET;
+		out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
+		udelay(1000);
+		tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
+		out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
+
+		/* Configure SRDSCR1 */
+		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
+		tmp &= ~FSL_SRDSCR1_PLLBW;
+		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
+
+		/* Configure SRDSCR2 */
+		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+		tmp &= ~FSL_SRDSCR2_SEIC_MASK;
+		tmp |= FSL_SRDSCR2_SEIC_SATA;
+		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+
+		/* Configure SRDSCR3 */
+		tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |
+			FSL_SRDSCR3_SDFM_SATA_PEX |
+			FSL_SRDSCR3_SDTXL_SATA;
+		out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
+
+		/* Configure SRDSCR4 */
+		tmp = rfcks | FSL_SRDSCR4_PROT_SATA;
+		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
+		break;
+	case FSL_SERDES_PROTO_PEX:
+	case FSL_SERDES_PROTO_PEX_X2:
+		/* Configure SRDSCR1 */
+		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
+		tmp |= FSL_SRDSCR1_PLLBW;
+		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
+
+		/* Configure SRDSCR2 */
+		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+		tmp &= ~FSL_SRDSCR2_SEIC_MASK;
+		tmp |= FSL_SRDSCR2_SEIC_PEX;
+		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+
+		/* Configure SRDSCR3 */
+		tmp = FSL_SRDSCR3_SDFM_SATA_PEX;
+		out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
+
+		/* Configure SRDSCR4 */
+		tmp = rfcks | FSL_SRDSCR4_PROT_PEX;
+		if (proto == FSL_SERDES_PROTO_PEX_X2)
+			tmp |= FSL_SRDSCR4_PLANE_X2;
+		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
+		break;
+	case FSL_SERDES_PROTO_SGMII:
+		/* Configure SRDSCR1 */
+		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
+		tmp &= ~FSL_SRDSCR1_PLLBW;
+		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
+
+		/* Configure SRDSCR2 */
+		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+		tmp &= ~FSL_SRDSCR2_SEIC_MASK;
+		tmp |= FSL_SRDSCR2_SEIC_SGMII;
+		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+
+		/* Configure SRDSCR3 */
+		out_be32(regs + FSL_SRDSCR3_OFFS, 0);
+
+		/* Configure SRDSCR4 */
+		tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;
+		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
+		break;
+	default:
+		return;
+	}
+
+	/* Do a software reset */
+	tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
+	tmp |= FSL_SRDSRSTCTL_RST;
+	out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
+}
+
+void fsl_setup_serdes(void)
+{
+#ifdef CONFIG_FSL_SERDES1
+	setup_serdes((void *)CONFIG_FSL_SERDES1, CONFIG_FSL_SERDES1_PROTO,
+		     CONFIG_FSL_SERDES1_CLK, CONFIG_FSL_SERDES1_VDD_1V);
+#endif
+#ifdef CONFIG_FSL_SERDES2
+	setup_serdes((void *)CONFIG_FSL_SERDES2, CONFIG_FSL_SERDES2_PROTO,
+		     CONFIG_FSL_SERDES2_CLK, CONFIG_FSL_SERDES2_VDD_1V);
+#endif
+}
diff --git a/include/asm-ppc/fsl_serdes.h b/include/asm-ppc/fsl_serdes.h
new file mode 100644
index 0000000..4c9a766
--- /dev/null
+++ b/include/asm-ppc/fsl_serdes.h
@@ -0,0 +1,25 @@
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+#ifdef CONFIG_FSL_SERDES
+
+#define FSL_SERDES_CLK_100		0
+#define FSL_SERDES_CLK_125		1
+#define FSL_SERDES_CLK_150		3
+#define FSL_SERDES_PROTO_SATA		0
+#define FSL_SERDES_PROTO_PEX		1
+#define FSL_SERDES_PROTO_PEX_X2		2
+#define FSL_SERDES_PROTO_SGMII		3
+#define FSL_SERDES_VDD1V		1
+
+extern void fsl_setup_serdes(void);
+
+#else
+
+static inline void fsl_setup_serdes(void) {}
+
+#endif
+
+#endif /* __FSL_SERDES_H */
-- 
1.5.2.2

[U-Boot-Users] [PATCH 3/7] 83xx: serdes setup routines

[Dave Liu]

On Sat, 2008-03-15 at 04:19 +0800, Anton Vorontsov wrote:
> This patch adds few routines to configure serdes on 837x targets.
> 
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

Kim, please apply it.

Thanks,
Dave

[U-Boot-Users] [PATCH 3/7] 83xx: serdes setup routines

[Jean-Christophe PLAGNIOL-VILLARD]

On 23:19 Fri 14 Mar     , Anton Vorontsov wrote:
> This patch adds few routines to configure serdes on 837x targets.
> 
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
>  cpu/mpc83xx/Makefile         |    1 +
>  cpu/mpc83xx/serdes.c         |  156 ++++++++++++++++++++++++++++++++++++++++++
>  include/asm-ppc/fsl_serdes.h |   25 +++++++
>  3 files changed, 182 insertions(+), 0 deletions(-)
>  create mode 100644 cpu/mpc83xx/serdes.c
>  create mode 100644 include/asm-ppc/fsl_serdes.h
> 
> diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
> index 7ad7e3e..6b6b027 100644
> --- a/cpu/mpc83xx/Makefile
> +++ b/cpu/mpc83xx/Makefile
> @@ -39,6 +39,7 @@ COBJS-y += ecc.o
>  COBJS-$(CONFIG_QE) += qe_io.o
>  COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
>  COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
> +COBJS-$(CONFIG_FSL_SERDES) += serdes.o
Please keep it sort

Best Regards,
J.

[U-Boot-Users] [PATCH 3/7] 83xx: serdes setup routines

[Anton Vorontsov]

On Tue, Mar 18, 2008 at 11:28:20AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 23:19 Fri 14 Mar     , Anton Vorontsov wrote:
> > This patch adds few routines to configure serdes on 837x targets.
> > 
> > Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> > ---
> >  cpu/mpc83xx/Makefile         |    1 +
> >  cpu/mpc83xx/serdes.c         |  156 ++++++++++++++++++++++++++++++++++++++++++
> >  include/asm-ppc/fsl_serdes.h |   25 +++++++
> >  3 files changed, 182 insertions(+), 0 deletions(-)
> >  create mode 100644 cpu/mpc83xx/serdes.c
> >  create mode 100644 include/asm-ppc/fsl_serdes.h
> > 
> > diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
> > index 7ad7e3e..6b6b027 100644
> > --- a/cpu/mpc83xx/Makefile
> > +++ b/cpu/mpc83xx/Makefile
> > @@ -39,6 +39,7 @@ COBJS-y += ecc.o
> >  COBJS-$(CONFIG_QE) += qe_io.o
> >  COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
> >  COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
> > +COBJS-$(CONFIG_FSL_SERDES) += serdes.o
> Please keep it sort

Keeping cobjs in alphabetical order sounds weird to me, plus as
far as I can see, current Makefile tried to keep things in this
(sane) order:

start.S
COBJS += core (traps, cpu)
COBJS += "less" important code (speed, sdram, ..)
COBJS += auxiliary/not so important (pci, fdt, ....)

[Almost] the same order in which the code will be executed.

Though, in this case I should place SERDES above FDT, near the PCI.


Anyhow, firstly I'd like to know what Kim is thinking about all
this?

-- 
Anton Vorontsov
email: cboumailru at gmail.com
irc://irc.freenode.net/bd2

[U-Boot-Users] [PATCH 3/7] 83xx: serdes setup routines

[Kim Phillips]

On Tue, 18 Mar 2008 16:52:29 +0300
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:

> On Tue, Mar 18, 2008 at 11:28:20AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 23:19 Fri 14 Mar     , Anton Vorontsov wrote:
> > > This patch adds few routines to configure serdes on 837x targets.
> > > 
> > > Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> > > ---
> > >  cpu/mpc83xx/Makefile         |    1 +
> > >  cpu/mpc83xx/serdes.c         |  156 ++++++++++++++++++++++++++++++++++++++++++
> > >  include/asm-ppc/fsl_serdes.h |   25 +++++++
> > >  3 files changed, 182 insertions(+), 0 deletions(-)
> > >  create mode 100644 cpu/mpc83xx/serdes.c
> > >  create mode 100644 include/asm-ppc/fsl_serdes.h
> > > 
> > > diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
> > > index 7ad7e3e..6b6b027 100644
> > > --- a/cpu/mpc83xx/Makefile
> > > +++ b/cpu/mpc83xx/Makefile
> > > @@ -39,6 +39,7 @@ COBJS-y += ecc.o
> > >  COBJS-$(CONFIG_QE) += qe_io.o
> > >  COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
> > >  COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
> > > +COBJS-$(CONFIG_FSL_SERDES) += serdes.o
> > Please keep it sort
> 
> Keeping cobjs in alphabetical order sounds weird to me, plus as
> far as I can see, current Makefile tried to keep things in this
> (sane) order:
> 
> start.S
> COBJS += core (traps, cpu)
> COBJS += "less" important code (speed, sdram, ..)
> COBJS += auxiliary/not so important (pci, fdt, ....)
> 
> [Almost] the same order in which the code will be executed.
> 
> Though, in this case I should place SERDES above FDT, near the PCI.
> 
> 
> Anyhow, firstly I'd like to know what Kim is thinking about all
> this?

sorry, I was out for a while.

I personally don't have a problem with COBJS not in alpha order.

Alpha order is something Wolfgang has brought up in the past, seemingly
more appropriately, i.e. for things like board names in the main
Makefile and MAKEALL.

Kim