From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anton Vorontsov Date: Mon, 24 Mar 2008 21:42:37 +0300 Subject: [U-Boot-Users] [PATCH 2/2] mpc83xx: MPC837XERDB: add support for PCI-Express Message-ID: <20080324184237.GB13282@localhost.localdomain> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This is largely based on the MDS boards' code (patch by Tony Li ). Signed-off-by: Anton Vorontsov --- board/freescale/mpc837xerdb/Makefile | 5 +- board/freescale/mpc837xerdb/mpc837xerdb.c | 13 ++++- board/freescale/mpc837xerdb/pcie.c | 87 +++++++++++++++++++++++++++++ include/configs/MPC837XERDB.h | 28 +++++++++ 4 files changed, 131 insertions(+), 2 deletions(-) create mode 100644 board/freescale/mpc837xerdb/pcie.c diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile index 5ec7a87..5d9e188 100644 --- a/board/freescale/mpc837xerdb/Makefile +++ b/board/freescale/mpc837xerdb/Makefile @@ -25,8 +25,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_PCIE) += pcie.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 70f52da..78e208f 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -19,7 +19,7 @@ #include #include #include - +#include "pcie.h" #if defined(CFG_DRAM_TEST) int @@ -170,6 +170,17 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ + immap_t *immr = (immap_t *)CFG_IMMR; + u32 part = in_be32(&immr->sysconf.spridr) >> 16; + + if (part != SPR_8379E_REV10 >> 16 && part != SPR_8379_REV10 >> 16) + pcie_init_board(); + + return 0; +} + /* * Miscellaneous late-boot configurations * diff --git a/board/freescale/mpc837xerdb/pcie.c b/board/freescale/mpc837xerdb/pcie.c new file mode 100644 index 0000000..2fba8b9 --- /dev/null +++ b/board/freescale/mpc837xerdb/pcie.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Tony Li + * Copyright (C) 2008 MontaVista Software, Inc. + * Anton Vorontsov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include + +static struct pci_region pci_regions_0[] = { + { + bus_start: CFG_PCIE1_MEM_BASE, + phys_start: CFG_PCIE1_MEM_PHYS, + size: CFG_PCIE1_MEM_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCIE1_IO_BASE, + phys_start: CFG_PCIE1_IO_PHYS, + size: CFG_PCIE1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +static struct pci_region pci_regions_1[] = { + { + bus_start: CFG_PCIE2_MEM_BASE, + phys_start: CFG_PCIE2_MEM_PHYS, + size: CFG_PCIE2_MEM_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCIE2_IO_BASE, + phys_start: CFG_PCIE2_IO_PHYS, + size: CFG_PCIE2_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pcie_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile sysconf83xx_t *sysconf = &immr->sysconf; + volatile law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *reg[] = { pci_regions_0, pci_regions_1 }; + extern void disable_addr_trans(void); /* start.S */ + + disable_addr_trans(); + + /* Configure the clock for PCIE controller */ + clk->sccr &= ~0x003C0000; + clk->sccr |= 0x00140000; + + /* Deassert the resets in the control register */ + sysconf->pecr1 = 0xE0008000; +#if !defined(CONFIG_PCIE_X2) + sysconf->pecr2 = 0xE0008000; +#endif + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + pcie_law[0].bar = CFG_PCIE1_BASE & LAWBAR_BAR; + pcie_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pcie_law[1].bar = CFG_PCIE2_BASE & LAWBAR_BAR; + pcie_law[1].ar = LBLAWAR_EN | LBLAWAR_512MB; + +#if defined(CONFIG_PCIE_X2) + mpc83xx_pcie_init(1, reg, 0); +#else + mpc83xx_pcie_init(2, reg, 0); +#endif +} diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 3b5d035..b628f38 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -31,8 +31,10 @@ #define CONFIG_MPC837XERDB 1 #define CONFIG_PCI 1 +#define CONFIG_PCIE 1 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R /* @@ -380,6 +382,32 @@ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#ifdef CONFIG_PCIE +#define CONFIG_83XX_GENERIC_PCIE 1 /* Use generic PCIE setup*/ + +/* PCIE address map */ +#define CFG_PCIE1_BASE 0xA0000000 +#define CFG_PCIE1_MEM_BASE CFG_PCIE1_BASE +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x10000000 +#define CFG_PCIE1_CFG_BASE (CFG_PCIE1_MEM_BASE + CFG_PCIE1_MEM_SIZE) +#define CFG_PCIE1_CFG_SIZE 0x01000000 +#define CFG_PCIE1_IO_BASE 0x0 +#define CFG_PCIE1_IO_PHYS (CFG_PCIE1_CFG_BASE + CFG_PCIE1_CFG_SIZE) +#define CFG_PCIE1_IO_SIZE 0x00800000 + +#define CFG_PCIE2_BASE 0xC0000000 +#define CFG_PCIE2_MEM_BASE CFG_PCIE2_BASE +#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE +#define CFG_PCIE2_MEM_SIZE 0x10000000 +#define CFG_PCIE2_CFG_BASE (CFG_PCIE2_MEM_BASE + CFG_PCIE2_MEM_SIZE) +#define CFG_PCIE2_CFG_SIZE 0x01000000 +#define CFG_PCIE2_IO_BASE 0x0 +#define CFG_PCIE2_IO_PHYS (CFG_PCIE2_CFG_BASE + CFG_PCIE2_CFG_SIZE) +#define CFG_PCIE2_IO_SIZE 0x00800000 + +#endif /* CONFIG_PCIE */ #endif /* CONFIG_PCI */ /* -- 1.5.2.2