[U-Boot-Users] PPC440EPx/sequoia TLB question...

[Stefan Roese <sr@denx.de>]

On Thursday 24 April 2008, Dave Littell wrote:
> Well, there's registers in that address space, not unlike other
> registers in other TLB entries (PCI, BCSR, etc.) that are marked
> Guarded.  I would think the same rationale would apply to the internal
> registers.

We should probably split this up in multiple TLB entries then. SRAM without G 
set and registers with G set.

> I need to go back and check the register settings for speculative
> accesses.  I seem to remember that there's a 440EPx Errata (actually,
> more than one) that has a workaround that turns off speculative
> instruction fetches.  Data speculative accesses may have gotten squashed
> in there as well, so it wouldn't matter what the TLB said if that's the
> case.
>
> >> Also the TLB entry for SDRAM marks it Guarded, but that?s one area I
> >> would think wouldn't need to be Guarded.
> >
> > This could be a mistake. Should work without G bis set too. Please give
> > it a try and send a patch to fix it, if it works fine.
>
> Hard to define "works fine" - this is the same 440EPx platform I'm
> asking about over in the embedded Linux mailing list.  I'm pretty sure
> the kernel doesn't flag SDRAM as Guarded,

Yes, and the 4xx code to dynamically set the SDRAM TLB's in the SPD code 
doesn't set it either. So it really isn't needed.

> but I'll give it a try to see 
> how it goes.

Thanks.

Best regards,
Stefan

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