From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stefan Roese <sr@denx.de>
Date: Thu, 24 Apr 2008 15:07:57 +0200
Subject: [U-Boot-Users] PPC440EPx/sequoia TLB question...
In-Reply-To: <1209038285.2946.17.camel@vader.jdub.homelinux.org>
References: <480EA8E1.4060207@verizon.net> <200804240728.44082.sr@denx.de>
	<1209038285.2946.17.camel@vader.jdub.homelinux.org>
Message-ID: <200804241507.58057.sr@denx.de>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Thursday 24 April 2008, Josh Boyer wrote:
> > > Hard to define "works fine" - this is the same 440EPx platform I'm
> > > asking about over in the embedded Linux mailing list.  I'm pretty sure
> > > the kernel doesn't flag SDRAM as Guarded,
> >
> > Yes, and the 4xx code to dynamically set the SDRAM TLB's in the SPD code
> > doesn't set it either. So it really isn't needed.
>
> Actually, that's not true for kernel memory.  We pin 256MiB TLBs to
> cover lowmem in AS0, and the Guarded bit is set.  We set it to prevent
> speculative access to memory holes where the 256MiB TLB covers more
> address space than there is physical DRAM.

I wasn't aware of this. Thanks for the explanation.

Best regards,
Stefan