From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Tue, 29 Apr 2008 11:42:52 +0200 Subject: [U-Boot-Users] [PATCH v2] PPC405EX(r) ECC and SDRAM Initialization Clean-ups In-Reply-To: <1209423587.8866.15.camel@duo> References: <1209423587.8866.15.camel@duo> Message-ID: <200804291142.53005.sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tuesday 29 April 2008, kenneth johansson wrote: > > > Stefan already asked this... I would also like to understand why the > > > data cache cannot be used for initial RAM as we do on so many other > > > systems? > > > > Agreed. The changes were based on the comments in the Kilauea and Makalu > > board ports indicating that this had been attempted--twice--and didn't > > work. > > > > I am escalating with AMCC to find out if this is a processor errata, > > board issue or just a programming issue that needs to be investigated > > further. > > The cache trick works fine on 405CR/405GP. Is the cache redesigned for > 405EX. Why would they still call it a 405 if the core was redesigned? I already sent an update to Grant privately on this. Here again: The main problem is that the board crashes with an exception (0x200: Data machine check) when init RAM in dcache is used. This happens upon calling trap_init() in board_init_r(). The exception must be pending and is "activated" upon the trap_init() call. Either Grant (or somebody else?) will look into this, or I will try to look into is (again) in a few days. Thanks. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================