[U-Boot-Users] [PATCH] PPC4xx: Add a non-EEPROM-driven SDRAM Initialization Function for the 405EX(r).

[U-Boot-Users] [PATCH] PPC4xx: Add a non-EEPROM-driven SDRAM Initialization Function for the 405EX(r).

[Grant Erickson]

This patch adds a non-EEPROM-driven SDRAM initialization function
driven by compile-time CFG_SDRAM_* parameters usable by 405EX(r)-based
boards that have discrete SDRAM chips rather than DIMMs.

This patch continues laying the ground work for moving out-of-assembly
and unifying the SDRAM initialization code for PowerPC 405EX[r]-based
boards.

Integration and unification of the EEPROM-driven version with this
parameter driven version may be tackled on another, later pass.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
---
 cpu/ppc4xx/44x_spd_ddr2.c |  126 ++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 120 insertions(+), 6 deletions(-)

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index ec76b71..c88d098 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -3,11 +3,14 @@
  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
  * DDR2 controller (non Denali Core). Those currently are:
  *
- * 405:		405EX
+ * 405:		405EX(r)
  * 440/460:	440SP/440SPe/460EX/460GT
  *
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+ *
+ * Copyright (c) 2007-2008 DENX Software Engineering, GmbH
+ *   Stefan Roese <sr@denx.de>
  *
  * COPYRIGHT   AMCC   CORPORATION 2004
  *
@@ -45,6 +48,10 @@
 #include <asm/mmu.h>
 #include <asm/cache.h>
 
+#if defined(CONFIG_DDR_ECC)
+#include "ecc.h"
+#endif
+
 #if defined(CONFIG_SPD_EEPROM) &&				\
 	(defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 	 defined(CONFIG_460EX) || defined(CONFIG_460GT))
@@ -3064,9 +3071,116 @@ static void ppc440sp_sdram_register_dump(void)
 	dcr_data = mfdcr(SDRAM_R3BAS);
 	printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
 }
-#else
+#else /* !defined(DEBUG) */
 static void ppc440sp_sdram_register_dump(void)
 {
 }
-#endif
-#endif /* CONFIG_SPD_EEPROM */
+#endif /* defined(DEBUG) */
+#elif defined(CONFIG_405EX)
+/*-----------------------------------------------------------------------------
+ * Function:	initdram
+ * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
+ * 		banks. The configuration is performed using static, compile-
+ *		time parameters.
+ *---------------------------------------------------------------------------*/
+long initdram(int board_type)
+{
+	unsigned long val;
+
+	/* Set Memory Bank Configuration Registers */
+
+	mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
+	mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
+	mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
+	mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
+
+	/* Set Memory Clock Timing Register */
+
+	mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
+
+	/* Set Refresh Time Register */
+
+	mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
+
+	/* Set SDRAM Timing Registers */
+
+	mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
+	mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
+	mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
+
+	/* Set Mode and Extended Mode Registers */
+
+	mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
+	mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
+
+	/* Set Memory Controller Options 1 Register */
+
+	mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
+
+	/* Set Manual Initialization Control Registers */
+
+	mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
+	mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
+	mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
+	mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
+	mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
+	mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
+	mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
+	mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
+	mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
+	mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
+	mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
+	mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
+	mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
+	mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
+	mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
+	mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
+
+	/* Set On-Die Termination Registers */
+
+	mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
+	mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
+	mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
+
+	/* Set Write Timing Register */
+
+	mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
+
+	/*
+	 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
+	 * SDRAM0_MCOPT2[IPTR] = 1
+	 */
+
+	mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT | 
+			       SDRAM_MCOPT2_IPTR_EXECUTE));
+
+	/*
+	 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
+	 * completion of initialization.
+	 */
+
+	do {
+		mfsdram(SDRAM_MCSTAT, val);
+	} while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
+
+	/* Set Delay Control Registers */
+
+	mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
+	mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
+	mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
+	mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
+
+	/*
+	 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
+	 */
+
+	mfsdram(SDRAM_MCOPT2, val);
+	mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
+
+#if defined(CONFIG_DDR_ECC)
+	ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+#endif /* defined(CONFIG_DDR_ECC) */
+
+	return (CFG_MBYTES_SDRAM << 20);
+}
+#endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */
-- 
1.5.4.3

[U-Boot-Users] [PATCH] PPC4xx: Add a non-EEPROM-driven SDRAM Initialization Function for the 405EX(r).

[Stefan Roese]

On Saturday 17 May 2008, Grant Erickson wrote:
> This patch adds a non-EEPROM-driven SDRAM initialization function
> driven by compile-time CFG_SDRAM_* parameters usable by 405EX(r)-based
> boards that have discrete SDRAM chips rather than DIMMs.
>
> This patch continues laying the ground work for moving out-of-assembly
> and unifying the SDRAM initialization code for PowerPC 405EX[r]-based
> boards.
>
> Integration and unification of the EEPROM-driven version with this
> parameter driven version may be tackled on another, later pass.

Good, thanks.

Please find some comments below.

> Signed-off-by: Grant Erickson <gerickson@nuovations.com>
> ---
>  cpu/ppc4xx/44x_spd_ddr2.c |  126
> ++++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 120
> insertions(+), 6 deletions(-)
>
> diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
> index ec76b71..c88d098 100644
> --- a/cpu/ppc4xx/44x_spd_ddr2.c
> +++ b/cpu/ppc4xx/44x_spd_ddr2.c
> @@ -3,11 +3,14 @@
>   * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
>   * DDR2 controller (non Denali Core). Those currently are:
>   *
> - * 405:		405EX
> + * 405:		405EX(r)
>   * 440/460:	440SP/440SPe/460EX/460GT
>   *
> - * (C) Copyright 2007-2008
> - * Stefan Roese, DENX Software Engineering, sr at denx.de.
> + * Copyright (c) 2008 Nuovation System Designs, LLC
> + *   Grant Erickson <gerickson@nuovations.com>
> + *
> + * Copyright (c) 2007-2008 DENX Software Engineering, GmbH
> + *   Stefan Roese <sr@denx.de>
>   *
>   * COPYRIGHT   AMCC   CORPORATION 2004
>   *
> @@ -45,6 +48,10 @@
>  #include <asm/mmu.h>
>  #include <asm/cache.h>
>
> +#if defined(CONFIG_DDR_ECC)
> +#include "ecc.h"
> +#endif

It should be save to remove this #ifdef.

>  #if defined(CONFIG_SPD_EEPROM) &&				\
>  	(defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
>  	 defined(CONFIG_460EX) || defined(CONFIG_460GT))
> @@ -3064,9 +3071,116 @@ static void ppc440sp_sdram_register_dump(void)
>  	dcr_data = mfdcr(SDRAM_R3BAS);
>  	printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
>  }
> -#else
> +#else /* !defined(DEBUG) */
>  static void ppc440sp_sdram_register_dump(void)
>  {
>  }
> -#endif
> -#endif /* CONFIG_SPD_EEPROM */
> +#endif /* defined(DEBUG) */
> +#elif defined(CONFIG_405EX)
> +/*------------------------------------------------------------------------
>----- + * Function:	initdram
> + * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
> + * 		banks. The configuration is performed using static, compile-
> + *		time parameters.
> +
> *--------------------------------------------------------------------------

Why is this block 405EX specific? This could be used on other 4xx variants 
using the same DDR2 controller, not?

And I'm wondering if this code really should go into this 
file "44x_spd_ddr2.c". Since now a 405 variant (405EX) can use this code too 
we should probably change the name to "4xx_spd_ddr2.c". And with this new 
fixed DDR2 init code it the SPD is not really fitting anymore. So the new 
name should probably be "4xx_ddr2.c".

Comments welcome.

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot-Users] [PATCH] PPC4xx: Add a non-EEPROM-driven SDRAM Initialization Function for the 405EX(r).

[Grant Erickson]

On 5/18/08 11:19 PM, Stefan Roese wrote:
>>  #if defined(CONFIG_SPD_EEPROM) &&    \
>> (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
>> defined(CONFIG_460EX) || defined(CONFIG_460GT))
>> @@ -3064,9 +3071,116 @@ static void ppc440sp_sdram_register_dump(void)
>> dcr_data = mfdcr(SDRAM_R3BAS);
>> printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
>>  }
>> -#else
>> +#else /* !defined(DEBUG) */
>>  static void ppc440sp_sdram_register_dump(void)
>>  {
>>  }
>> -#endif
>> -#endif /* CONFIG_SPD_EEPROM */
>> +#endif /* defined(DEBUG) */
>> +#elif defined(CONFIG_405EX)
>> +/*------------------------------------------------------------------------
>> ----- + * Function: initdram
>> + * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
>> + *   banks. The configuration is performed using static, compile-
>> + *  time parameters.
>> +
>> *--------------------------------------------------------------------------
> 
> Why is this block 405EX specific? This could be used on other 4xx variants
> using the same DDR2 controller, not?

The scope of my visibility is limited, so I punted on this first pass
attempt. More appropriate might have been CONFIG_DDR2_PARAMS vs.
CONFIG_DDR2_EEPROM or CONFIG_DDR2_AUTO.

> And I'm wondering if this code really should go into this
> file "44x_spd_ddr2.c". Since now a 405 variant (405EX) can use this code too
> we should probably change the name to "4xx_spd_ddr2.c". And with this new
> fixed DDR2 init code it the SPD is not really fitting anymore. So the new
> name should probably be "4xx_ddr2.c".
> 
> Comments welcome.

This controller works with both DDR and DDR2 memories, so that might be
misleading. What I'd like to see is a move away from processor-based CONFIG_
and towards feature-based CONFIG_. In that way, we can avoid ever-growing
lists like:

    #if defined(CONFIG_PPCX) || defined(CONFIG_PPCY) || defined(CONFIG_PPCZ)

However, what's needed then are convenient mnemonics for various
cores/blocks. EMAC works well enough for that block. However, DDR/DDR2/SDRAM
seem too generic. Does AMCC call this block something internally that's
leaked out? I see "Denali" used for one memory controller core, correct? Or
is that a board name?

Regards,

Grant
Principal
Nuovation System Designs, LLC

998 Alpine Terrace Suite 3
Sunnyvale, CA 94086-2469
US

T +1-408-749-0495
F +1-205-449-0495
M +1-408-489-5710

gerickson at nuovations.com
http://www.nuovations.com/

[U-Boot-Users] [PATCH] PPC4xx: Add a non-EEPROM-driven SDRAM Initialization Function for the 405EX(r).

[Stefan Roese]

On Monday 19 May 2008, Grant Erickson wrote:
> > And I'm wondering if this code really should go into this
> > file "44x_spd_ddr2.c". Since now a 405 variant (405EX) can use this code
> > too we should probably change the name to "4xx_spd_ddr2.c". And with this
> > new fixed DDR2 init code it the SPD is not really fitting anymore. So the
> > new name should probably be "4xx_ddr2.c".
> >
> > Comments welcome.
>
> This controller works with both DDR and DDR2 memories, so that might be
> misleading.

Right. But we need to differentiate from the "DDR only" controller used on 
440GP/GX/EP/GR.

> What I'd like to see is a move away from processor-based 
> CONFIG_ and towards feature-based CONFIG_. In that way, we can avoid
> ever-growing lists like:
>
>     #if defined(CONFIG_PPCX) || defined(CONFIG_PPCY) ||
> defined(CONFIG_PPCZ)

Full ack.

> However, what's needed then are convenient mnemonics for various
> cores/blocks. EMAC works well enough for that block. However,
> DDR/DDR2/SDRAM seem too generic. Does AMCC call this block something
> internally that's leaked out? I see "Denali" used for one memory controller
> core, correct? Or is that a board name? 

Denali is the name of the DDR(2) controller core IP supplier used on 440EPx 
etc. Since the "other" DDR(2) controller core comes from IBM, we should 
probably name it "4xx_ibm_ddr2.c". Not sure about ddr2 vs. ddr though.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================